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Received-SPF: pass client-ip=80.78.11.84; envelope-from=clement.mathieu--drif@eviden.com; helo=smarthost3.eviden.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @eviden.com) X-ZM-MESSAGEID: 1732866276343019100 From: Cl=C3=A9ment Mathieu--Drif Signed-off-by: Cl=C3=A9ment Mathieu--Drif --- hw/pci/pcie.c | 24 ++++++++++++++++++++++++ include/hw/pci/pcie.h | 6 +++++- include/hw/pci/pcie_regs.h | 5 +++++ 3 files changed, 34 insertions(+), 1 deletion(-) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 0b455c8654..5b896496ae 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -1210,3 +1210,27 @@ void pcie_acs_reset(PCIDevice *dev) pci_set_word(dev->config + dev->exp.acs_cap + PCI_ACS_CTRL, 0); } } + +/* PASID */ +void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width, + bool exec_perm, bool priv_mod) +{ + assert(pasid_width <=3D PCI_EXT_CAP_PASID_MAX_WIDTH); + static const uint16_t control_reg_rw_mask =3D 0x07; + uint16_t capability_reg =3D pasid_width; + + pcie_add_capability(dev, PCI_EXT_CAP_ID_PASID, PCI_PASID_VER, offset, + PCI_EXT_CAP_PASID_SIZEOF); + + capability_reg <<=3D PCI_PASID_CAP_WIDTH_SHIFT; + capability_reg |=3D exec_perm ? PCI_PASID_CAP_EXEC : 0; + capability_reg |=3D priv_mod ? PCI_PASID_CAP_PRIV : 0; + pci_set_word(dev->config + offset + PCI_PASID_CAP, capability_reg); + + /* Everything is disabled by default */ + pci_set_word(dev->config + offset + PCI_PASID_CTRL, 0); + + pci_set_word(dev->wmask + offset + PCI_PASID_CTRL, control_reg_rw_mask= ); + + dev->exp.pasid_cap =3D offset; +} diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index b8d59732bc..aa040c3e97 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -72,8 +72,9 @@ struct PCIExpressDevice { uint16_t aer_cap; PCIEAERLog aer_log; =20 - /* Offset of ATS capability in config space */ + /* Offset of ATS and PASID capabilities in config space */ uint16_t ats_cap; + uint16_t pasid_cap; =20 /* ACS */ uint16_t acs_cap; @@ -152,4 +153,7 @@ void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_de= v, DeviceState *dev, Error **errp); void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp); + +void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width, + bool exec_perm, bool priv_mod); #endif /* QEMU_PCIE_H */ diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h index 9d3b6868dc..4d9cf4a29c 100644 --- a/include/hw/pci/pcie_regs.h +++ b/include/hw/pci/pcie_regs.h @@ -86,6 +86,11 @@ typedef enum PCIExpLinkWidth { #define PCI_ARI_VER 1 #define PCI_ARI_SIZEOF 8 =20 +/* PASID */ +#define PCI_PASID_VER 1 +#define PCI_EXT_CAP_PASID_MAX_WIDTH 20 +#define PCI_PASID_CAP_WIDTH_SHIFT 8 + /* AER */ #define PCI_ERR_VER 2 #define PCI_ERR_SIZEOF 0x48 --=20 2.47.0