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helo=lists.gnu.org; Received-SPF: pass client-ip=80.78.11.83; envelope-from=clement.mathieu--drif@eviden.com; helo=smarthost2.eviden.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @eviden.com) X-ZM-MESSAGEID: 1732866288067019100 From: Cl=C3=A9ment Mathieu--Drif Implements the behavior defined in section 10.2.3.5 of PCIe spec rev 5. This is needed by devices that support ATS. Signed-off-by: Cl=C3=A9ment Mathieu--Drif --- hw/i386/intel_iommu.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 7e8676efb0..0637437552 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2100,7 +2100,8 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *v= td_as, PCIBus *bus, uint8_t bus_num =3D pci_bus_num(bus); VTDContextCacheEntry *cc_entry; uint64_t pte, page_mask; - uint32_t level, pasid =3D vtd_as->pasid; + uint32_t level =3D UINT32_MAX; + uint32_t pasid =3D vtd_as->pasid; uint16_t source_id =3D PCI_BUILD_BDF(bus_num, devfn); int ret_fr; bool is_fpd_set =3D false; @@ -2262,7 +2263,7 @@ out: entry->iova =3D addr & page_mask; entry->translated_addr =3D vtd_get_pte_addr(pte, s->aw_bits) & page_ma= sk; entry->addr_mask =3D ~page_mask; - entry->perm =3D access_flags; + entry->perm =3D (is_write ? access_flags : (access_flags & (~IOMMU_WO)= )); /* pasid already set */ return true; =20 @@ -2270,7 +2271,12 @@ error: vtd_iommu_unlock(s); entry->iova =3D 0; entry->translated_addr =3D 0; - entry->addr_mask =3D 0; + /* + * Set the mask for ATS (the range must be present even when the + * translation fails : PCIe rev 5 10.2.3.5) + */ + entry->addr_mask =3D (level !=3D UINT32_MAX) ? + (~vtd_pt_level_page_mask(level)) : (~VTD_PAGE_MASK_= 4K); entry->perm =3D IOMMU_NONE; entry->pasid =3D PCI_NO_PASID; return false; --=20 2.47.0