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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-215218f452csm13829005ad.48.2024.11.28.06.12.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 06:13:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1732803182; x=1733407982; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C4JUFLTOJhJslmXjXCGh+2VEFVmYCejzSQzv/yR+Yn0=; b=vIkFETEstjkOlotQ7m8WscOZeWQd0wUhXoRCJVt7MnxHfzMU4R/wuVJHnzRrNbOFs+ 0CZGGhD3NBlka+OxSxst3ZD0z6e/Trz8omCHXqnUYtD4rA2GZIw2kVxTwmLVajJ3g6zK qnconk+tf/JhHiT3wt+Hd2mq0inrXXZ+3cbFxBEDurE9Zlxajk+krpZsV01TeIr/0GjB ZmQLW6MCRip15rY2VNRW926oj+NE9/T1Is8JiX3ZG5W3bUCETarI42CbnnubBAAssfRX NomHEnhl8ddJ+Ma/gveXciF0cIIX1KmkvE+7PRdPbX9BW5lk8g9ESaBWLCAZbuWmj6dF yzwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732803182; x=1733407982; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C4JUFLTOJhJslmXjXCGh+2VEFVmYCejzSQzv/yR+Yn0=; b=J44DqBGBBW/xD9XXfS7zQbLnpYcSzU+t8m8M2nNiRmYRZXfH0jIqXyFueES9FncGlW oAJVkedz3VSLI25awrNtD8MyyR6I4iDJMIzO2TGtyMTFMMAEoxp0ehBnsi88U8bGRHG9 vSalk4gXydvqlKOn6aGeDbXPmaYRgp5MmrdM8q2/yLnSnfznViy+wjt9bZZ0NakIlej2 EDi1gOQdTRDB/Ozjwvx3V72kQNj2OzdiW7epaGb6k+A3YXDJ/6HuvwEyH0k8aEGZwYo+ ZzTvhq28JJGD6ui/KthkU9mEUehQJ72PtYkBS6EiySEAQbDPwMTJeN7mToG4WPg1FOU9 AJOw== X-Forwarded-Encrypted: i=1; AJvYcCXYUgLRqil50bVFD+t/cV+7HS2wM2mp/FUeZGNdL1caMmnmek7zx50GtBJfwcyxZWV1TFelmrXqAG4A@nongnu.org X-Gm-Message-State: AOJu0Ywc/GkjYKSHwKLi8QIWXf3sdb6U6Ir4PcvAPi+/pOR245nL/m1G bpxg4M3seynjTV4BCkv2H1whnCyWeOSke+zBSd3qhF+hori9Bl5Jupz6vmVyoNE= X-Gm-Gg: ASbGncvpkqm9/mi7uCDoKCvdKquL9VHY4dYOesIjzXgr8IG6oHNRhnynxDC1nA40pLH p/mu13mYRluWY4OGq6rrblMOk1I4NBdPLUUggoemQ/j2XOOKgXN+OmP4XYAPcqu7vAaXlG6gMAQ 3WB+s3Vz7WnxRf6dcBuQQPKgz+Z26mrJnFJRM9+BYoHOgBLPPyPAaDfSlXt8LAS+Afy6tDB0jkM zJjhScTTkhe+Efapbyy4I1+aRojV902hS1hmPdfY9lJRt7593Y= X-Google-Smtp-Source: AGHT+IEBvrCQoPSVZ9VjdSgKjU7C86n9zuigE2JYsVRZBB5oQ1RemhVbYcsZR4FVdgb24Mqkqw2tiQ== X-Received: by 2002:a17:902:ea08:b0:212:63db:bb15 with SMTP id d9443c01a7336-21501b593b5mr106675755ad.38.1732803182166; Thu, 28 Nov 2024 06:13:02 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ved Shanbhogue , Atish Patra , qemu-devel@nongnu.org, Frank Chang Subject: [PATCH v6 1/9] target/riscv: fix henvcfg potentially containing stale bits Date: Thu, 28 Nov 2024 15:12:21 +0100 Message-ID: <20241128141230.284320-2-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241128141230.284320-1-cleger@rivosinc.com> References: <20241128141230.284320-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=cleger@rivosinc.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1732803326782019100 With the current implementation, if we had the following scenario: - Set bit x in menvcfg - Set bit x in henvcfg - Clear bit x in menvcfg then, the internal variable env->henvcfg would still contain bit x due to both a wrong menvcfg mask used in write_henvcfg() as well as a missing update of henvcfg upon menvcfg update. This can lead to some wrong interpretation of the context. In order to update henvcfg upon menvcfg writing, call write_henvcfg() after writing menvcfg. Clearing henvcfg upon writing the new value is also needed in write_henvcfg() as well as clearing henvcfg upper part when writing it with write_henvcfgh(). Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/csr.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5d8d0d7514..98c683df60 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2383,6 +2383,8 @@ static RISCVException read_menvcfg(CPURISCVState *env= , int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException write_henvcfg(CPURISCVState *env, int csrno, + target_ulong val); static RISCVException write_menvcfg(CPURISCVState *env, int csrno, target_ulong val) { @@ -2403,6 +2405,7 @@ static RISCVException write_menvcfg(CPURISCVState *en= v, int csrno, } } env->menvcfg =3D (env->menvcfg & ~mask) | (val & mask); + write_henvcfg(env, CSR_HENVCFG, env->henvcfg); =20 return RISCV_EXCP_NONE; } @@ -2414,6 +2417,8 @@ static RISCVException read_menvcfgh(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, + target_ulong val); static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, target_ulong val) { @@ -2424,6 +2429,7 @@ static RISCVException write_menvcfgh(CPURISCVState *e= nv, int csrno, uint64_t valh =3D (uint64_t)val << 32; =20 env->menvcfg =3D (env->menvcfg & ~mask) | (valh & mask); + write_henvcfgh(env, CSR_HENVCFGH, env->henvcfg >> 32); =20 return RISCV_EXCP_NONE; } @@ -2513,7 +2519,7 @@ static RISCVException write_henvcfg(CPURISCVState *en= v, int csrno, } } =20 - env->henvcfg =3D (env->henvcfg & ~mask) | (val & mask); + env->henvcfg =3D val & mask; =20 return RISCV_EXCP_NONE; } @@ -2546,7 +2552,7 @@ static RISCVException write_henvcfgh(CPURISCVState *e= nv, int csrno, return ret; } =20 - env->henvcfg =3D (env->henvcfg & ~mask) | (valh & mask); + env->henvcfg =3D (env->henvcfg & 0xFFFFFFFF) | (valh & mask); return RISCV_EXCP_NONE; } =20 --=20 2.45.2 From nobody Thu Dec 26 21:33:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1732803294; cv=none; d=zohomail.com; s=zohoarc; b=IWlkHcycNRI3zCfIhGjJ/KnClfGjIOFpB7twIglUEX9cXnu8LkySGMCmHFSFOZtJig295CvU1jEc44mzNgczu8y/a+HXI6257jTkDfTXtv/Iaq1xxGZ40J0Q4rFMI3f8TyiRcqQe9SBzvjF3F0fToLI6FHg3tRAzDr/LTZlWtvc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1732803294; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=XceK4BjQwIlZ4xVaLaVwHcOHKVnH+FfCQgwz0Xbj0CU=; b=cNwD/YeDCOkETsvdvfQhzVauAuib02buz1aDrirPsu5y9PvbwOiyPPfrPuYkiGMlxmoE0yPyllFDddtBYDK8Q4A0knBuPMl38LohYwq/MEb23Zm7Wp0Zz1Knh7LL+zBigpvXv3Kn33zhi5drCvo3QAaUV99aOSxF+0MB9pfsAX8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1732803294604380.60816278104755; Thu, 28 Nov 2024 06:14:54 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tGfGf-00057J-VC; Thu, 28 Nov 2024 09:13:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tGfGc-00056k-Kp for qemu-devel@nongnu.org; Thu, 28 Nov 2024 09:13:14 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tGfGa-0005ss-De for qemu-devel@nongnu.org; Thu, 28 Nov 2024 09:13:14 -0500 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-21288ce11d7so7622355ad.2 for ; Thu, 28 Nov 2024 06:13:10 -0800 (PST) Received: from carbon-x1.. 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Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 6 ++++ target/riscv/cpu_cfg.h | 1 + target/riscv/cpu_helper.c | 17 +++++++++ target/riscv/csr.c | 72 ++++++++++++++++++++++++++++++++------- 5 files changed, 84 insertions(+), 13 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8dc5b4d002..02e502768e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -569,6 +569,7 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, boo= l enable); int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); bool cpu_get_fcfien(CPURISCVState *env); bool cpu_get_bcfien(CPURISCVState *env); +bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt); G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t reta= ddr); diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index f31735d15b..dcf63b7f32 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -562,6 +562,7 @@ #define MSTATUS_TW 0x00200000 /* since: priv-1.10 */ #define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */ #define MSTATUS_SPELP 0x00800000 /* zicfilp */ +#define MSTATUS_SDT 0x01000000 #define MSTATUS_MPELP 0x020000000000 /* zicfilp */ #define MSTATUS_GVA 0x4000000000ULL #define MSTATUS_MPV 0x8000000000ULL @@ -594,6 +595,7 @@ typedef enum { #define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */ #define SSTATUS_MXR 0x00080000 #define SSTATUS_SPELP MSTATUS_SPELP /* zicfilp */ +#define SSTATUS_SDT MSTATUS_SDT =20 #define SSTATUS64_UXL 0x0000000300000000ULL =20 @@ -791,11 +793,13 @@ typedef enum RISCVException { #define MENVCFG_CBIE (3UL << 4) #define MENVCFG_CBCFE BIT(6) #define MENVCFG_CBZE BIT(7) +#define MENVCFG_DTE (1ULL << 59) #define MENVCFG_ADUE (1ULL << 61) #define MENVCFG_PBMTE (1ULL << 62) #define MENVCFG_STCE (1ULL << 63) =20 /* For RV32 */ +#define MENVCFGH_DTE BIT(27) #define MENVCFGH_ADUE BIT(29) #define MENVCFGH_PBMTE BIT(30) #define MENVCFGH_STCE BIT(31) @@ -813,11 +817,13 @@ typedef enum RISCVException { #define HENVCFG_CBIE MENVCFG_CBIE #define HENVCFG_CBCFE MENVCFG_CBCFE #define HENVCFG_CBZE MENVCFG_CBZE +#define HENVCFG_DTE MENVCFG_DTE #define HENVCFG_ADUE MENVCFG_ADUE #define HENVCFG_PBMTE MENVCFG_PBMTE #define HENVCFG_STCE MENVCFG_STCE =20 /* For RV32 */ +#define HENVCFGH_DTE MENVCFGH_DTE #define HENVCFGH_ADUE MENVCFGH_ADUE #define HENVCFGH_PBMTE MENVCFGH_PBMTE #define HENVCFGH_STCE MENVCFGH_STCE diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 321f64fd72..1194dfd3bc 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -79,6 +79,7 @@ struct RISCVCPUConfig { bool ext_smstateen; bool ext_sstc; bool ext_smcntrpmf; + bool ext_ssdbltrp; bool ext_svadu; bool ext_svinval; bool ext_svnapot; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d53ddc384f..3fabd3379c 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -120,6 +120,19 @@ bool cpu_get_bcfien(CPURISCVState *env) } } =20 +bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt) +{ +#ifdef CONFIG_USER_ONLY + return false; +#else + if (virt) { + return (env->henvcfg & HENVCFG_DTE) !=3D 0; + } else { + return (env->menvcfg & MENVCFG_DTE) !=3D 0; + } +#endif +} + void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, uint64_t *cs_base, uint32_t *pflags) { @@ -642,6 +655,10 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) =20 g_assert(riscv_has_ext(env, RVH)); =20 + if (riscv_env_smode_dbltrp_enabled(env, current_virt)) { + mstatus_mask |=3D MSTATUS_SDT; + } + if (current_virt) { /* Current V=3D1 and we are about to change to V=3D0 */ env->vsstatus =3D env->mstatus & mstatus_mask; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 98c683df60..611f44e044 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -559,6 +559,15 @@ static RISCVException aia_hmode32(CPURISCVState *env, = int csrno) return hmode32(env, csrno); } =20 +static RISCVException dbltrp_hmode(CPURISCVState *env, int csrno) +{ + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + return RISCV_EXCP_NONE; + } + + return hmode(env, csrno); +} + static RISCVException pmp(CPURISCVState *env, int csrno) { if (riscv_cpu_cfg(env)->pmp) { @@ -1633,6 +1642,13 @@ static RISCVException write_mstatus(CPURISCVState *e= nv, int csrno, mask |=3D MSTATUS_VS; } =20 + if (riscv_env_smode_dbltrp_enabled(env, env->virt_enabled)) { + mask |=3D MSTATUS_SDT; + if ((val & MSTATUS_SDT) !=3D 0) { + val &=3D ~MSTATUS_SIE; + } + } + if (xl !=3D MXL_RV32 || env->debugger) { if (riscv_has_ext(env, RVH)) { mask |=3D MSTATUS_MPV | MSTATUS_GVA; @@ -2394,7 +2410,8 @@ static RISCVException write_menvcfg(CPURISCVState *en= v, int csrno, if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { mask |=3D (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) | - (cfg->ext_svadu ? MENVCFG_ADUE : 0); + (cfg->ext_svadu ? MENVCFG_ADUE : 0) | + (cfg->ext_ssdbltrp ? MENVCFG_DTE : 0); =20 if (env_archcpu(env)->cfg.ext_zicfilp) { mask |=3D MENVCFG_LPE; @@ -2403,6 +2420,10 @@ static RISCVException write_menvcfg(CPURISCVState *e= nv, int csrno, if (env_archcpu(env)->cfg.ext_zicfiss) { mask |=3D MENVCFG_SSE; } + + if ((val & MENVCFG_DTE) =3D=3D 0) { + env->mstatus &=3D ~MSTATUS_SDT; + } } env->menvcfg =3D (env->menvcfg & ~mask) | (val & mask); write_henvcfg(env, CSR_HENVCFG, env->henvcfg); @@ -2425,9 +2446,14 @@ static RISCVException write_menvcfgh(CPURISCVState *= env, int csrno, const RISCVCPUConfig *cfg =3D riscv_cpu_cfg(env); uint64_t mask =3D (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) | - (cfg->ext_svadu ? MENVCFG_ADUE : 0); + (cfg->ext_svadu ? MENVCFG_ADUE : 0) | + (cfg->ext_ssdbltrp ? MENVCFG_DTE : 0); uint64_t valh =3D (uint64_t)val << 32; =20 + if ((valh & MENVCFG_DTE) =3D=3D 0) { + env->mstatus &=3D ~MSTATUS_SDT; + } + env->menvcfg =3D (env->menvcfg & ~mask) | (valh & mask); write_henvcfgh(env, CSR_HENVCFGH, env->henvcfg >> 32); =20 @@ -2488,9 +2514,10 @@ static RISCVException read_henvcfg(CPURISCVState *en= v, int csrno, * henvcfg.pbmte is read_only 0 when menvcfg.pbmte =3D 0 * henvcfg.stce is read_only 0 when menvcfg.stce =3D 0 * henvcfg.adue is read_only 0 when menvcfg.adue =3D 0 + * henvcfg.dte is read_only 0 when menvcfg.dte =3D 0 */ - *val =3D env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE= ) | - env->menvcfg); + *val =3D env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE= | + HENVCFG_DTE) | env->menvcfg); return RISCV_EXCP_NONE; } =20 @@ -2506,7 +2533,8 @@ static RISCVException write_henvcfg(CPURISCVState *en= v, int csrno, } =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { - mask |=3D env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_A= DUE); + mask |=3D env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_A= DUE | + HENVCFG_DTE); =20 if (env_archcpu(env)->cfg.ext_zicfilp) { mask |=3D HENVCFG_LPE; @@ -2520,6 +2548,9 @@ static RISCVException write_henvcfg(CPURISCVState *en= v, int csrno, } =20 env->henvcfg =3D val & mask; + if ((env->henvcfg & HENVCFG_DTE) =3D=3D 0) { + env->vsstatus &=3D ~MSTATUS_SDT; + } =20 return RISCV_EXCP_NONE; } @@ -2534,8 +2565,8 @@ static RISCVException read_henvcfgh(CPURISCVState *en= v, int csrno, return ret; } =20 - *val =3D (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADU= E) | - env->menvcfg)) >> 32; + *val =3D (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADU= E | + HENVCFG_DTE) | env->menvcfg)) >> 32; return RISCV_EXCP_NONE; } =20 @@ -2543,7 +2574,7 @@ static RISCVException write_henvcfgh(CPURISCVState *e= nv, int csrno, target_ulong val) { uint64_t mask =3D env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | - HENVCFG_ADUE); + HENVCFG_ADUE | HENVCFG_DTE); uint64_t valh =3D (uint64_t)val << 32; RISCVException ret; =20 @@ -2551,8 +2582,10 @@ static RISCVException write_henvcfgh(CPURISCVState *= env, int csrno, if (ret !=3D RISCV_EXCP_NONE) { return ret; } - env->henvcfg =3D (env->henvcfg & 0xFFFFFFFF) | (valh & mask); + if ((env->henvcfg & HENVCFG_DTE) =3D=3D 0) { + env->vsstatus &=3D ~MSTATUS_SDT; + } return RISCV_EXCP_NONE; } =20 @@ -2980,6 +3013,9 @@ static RISCVException read_sstatus_i128(CPURISCVState= *env, int csrno, if (env->xl !=3D MXL_RV32 || env->debugger) { mask |=3D SSTATUS64_UXL; } + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + mask |=3D SSTATUS_SDT; + } =20 if (env_archcpu(env)->cfg.ext_zicfilp) { mask |=3D SSTATUS_SPELP; @@ -2996,11 +3032,12 @@ static RISCVException read_sstatus(CPURISCVState *e= nv, int csrno, if (env->xl !=3D MXL_RV32 || env->debugger) { mask |=3D SSTATUS64_UXL; } - if (env_archcpu(env)->cfg.ext_zicfilp) { mask |=3D SSTATUS_SPELP; } - + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + mask |=3D SSTATUS_SDT; + } /* TODO: Use SXL not MXL. */ *val =3D add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); return RISCV_EXCP_NONE; @@ -3020,7 +3057,9 @@ static RISCVException write_sstatus(CPURISCVState *en= v, int csrno, if (env_archcpu(env)->cfg.ext_zicfilp) { mask |=3D SSTATUS_SPELP; } - + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + mask |=3D SSTATUS_SDT; + } target_ulong newval =3D (env->mstatus & ~mask) | (val & mask); return write_mstatus(env, CSR_MSTATUS, newval); } @@ -4126,6 +4165,13 @@ static RISCVException write_vsstatus(CPURISCVState *= env, int csrno, if ((val & VSSTATUS64_UXL) =3D=3D 0) { mask &=3D ~VSSTATUS64_UXL; } + if ((env->henvcfg & HENVCFG_DTE)) { + if ((val & SSTATUS_SDT) !=3D 0) { + val &=3D ~SSTATUS_SIE; + } + } else { + val &=3D ~SSTATUS_SDT; + } env->vsstatus =3D (env->vsstatus & ~mask) | (uint64_t)val; return RISCV_EXCP_NONE; } @@ -5336,7 +5382,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_VSATP] =3D { "vsatp", hmode, read_vsatp, write_v= satp, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, =20 - [CSR_MTVAL2] =3D { "mtval2", hmode, read_mtval2, write_m= tval2, + [CSR_MTVAL2] =3D { "mtval2", dbltrp_hmode, read_mtval2, write_mtv= al2, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MTINST] =3D { "mtinst", hmode, read_mtinst, write_m= tinst, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, --=20 2.45.2 From nobody Thu Dec 26 21:33:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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When executing mret/mnret, SSTATUS.SDT is cleared when returning to U, VS or VU and VSSTATUS.SDT is cleared when returning to VU from HS. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Alistair Francis --- target/riscv/op_helper.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index a4b625fcd9..eeacb2d1a1 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -287,6 +287,18 @@ target_ulong helper_sret(CPURISCVState *env) get_field(mstatus, MSTATUS_SPIE)); mstatus =3D set_field(mstatus, MSTATUS_SPIE, 1); mstatus =3D set_field(mstatus, MSTATUS_SPP, PRV_U); + + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + if (riscv_has_ext(env, RVH)) { + target_ulong prev_vu =3D get_field(env->hstatus, HSTATUS_SPV) = && + prev_priv =3D=3D PRV_U; + /* Returning to VU from HS, vsstatus.sdt =3D 0 */ + if (!env->virt_enabled && prev_vu) { + env->vsstatus =3D set_field(env->vsstatus, MSTATUS_SDT, 0); + } + } + mstatus =3D set_field(mstatus, MSTATUS_SDT, 0); + } if (env->priv_ver >=3D PRIV_VERSION_1_12_0) { mstatus =3D set_field(mstatus, MSTATUS_MPRV, 0); } @@ -297,7 +309,6 @@ target_ulong helper_sret(CPURISCVState *env) target_ulong hstatus =3D env->hstatus; =20 prev_virt =3D get_field(hstatus, HSTATUS_SPV); - hstatus =3D set_field(hstatus, HSTATUS_SPV, 0); =20 env->hstatus =3D hstatus; @@ -337,6 +348,22 @@ static void check_ret_from_m_mode(CPURISCVState *env, = target_ulong retpc, riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC()); } } +static target_ulong ssdbltrp_mxret(CPURISCVState *env, target_ulong mstatu= s, + target_ulong prev_priv, + target_ulong prev_virt) +{ + /* If returning to U, VS or VU, sstatus.sdt =3D 0 */ + if (prev_priv =3D=3D PRV_U || (prev_virt && + (prev_priv =3D=3D PRV_S || prev_priv =3D=3D PRV_U))) { + mstatus =3D set_field(mstatus, MSTATUS_SDT, 0); + /* If returning to VU, vsstatus.sdt =3D 0 */ + if (prev_virt && prev_priv =3D=3D PRV_U) { + env->vsstatus =3D set_field(env->vsstatus, MSTATUS_SDT, 0); + } + } + + return mstatus; +} =20 target_ulong helper_mret(CPURISCVState *env) { @@ -354,6 +381,9 @@ target_ulong helper_mret(CPURISCVState *env) mstatus =3D set_field(mstatus, MSTATUS_MPP, riscv_has_ext(env, RVU) ? PRV_U : PRV_M); mstatus =3D set_field(mstatus, MSTATUS_MPV, 0); + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + mstatus =3D ssdbltrp_mxret(env, mstatus, prev_priv, prev_virt); + } if ((env->priv_ver >=3D PRIV_VERSION_1_12_0) && (prev_priv !=3D PRV_M)= ) { mstatus =3D set_field(mstatus, MSTATUS_MPRV, 0); } @@ -395,6 +425,9 @@ target_ulong helper_mnret(CPURISCVState *env) if (prev_priv < PRV_M) { env->mstatus =3D set_field(env->mstatus, MSTATUS_MPRV, false); } + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + env->mstatus =3D ssdbltrp_mxret(env, env->mstatus, prev_priv, prev= _virt); + } =20 if (riscv_has_ext(env, RVH) && prev_virt) { riscv_cpu_swap_hypervisor_regs(env); --=20 2.45.2 From nobody Thu Dec 26 21:33:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1732803305; cv=none; d=zohomail.com; s=zohoarc; b=XYFzEc5YvMAYFf3xl6lNaK83/J9Q8FDR0z8BbYHStg7dh0ye9IBUQtN3MifZ0cutC8OIKxOO/Wi/i1YwY8+JYb8wo7/dX+P6SXwGnlRPd0obPM3L8665aRyrpXFAXGH6nkpYPXgEX1+hBmlrSKnMfrIKWnQnEJDTj37dLH9F74I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1732803305; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=jFc6IlNRnNduu1qhiN6zUJvi9doVv2GL0KddS1ZLVCE=; b=IgzpW+M2BLK5XyAC64OwV9yrMPWihoOvS/5FvsFgI++u1b6aZi6BmbYaXq8Mdw8ZBErKE3x4JBucN/f3epUIe8V01Zde8Y7xcDwdATJQvL0vS121euy3TfhJ3oqTlFWUsjT388MCiXRdZEa7P4vFewDnnqNJneBHE4EzDjy+/hE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1732803305117923.5957179647736; Thu, 28 Nov 2024 06:15:05 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tGfGq-0005AA-DL; Thu, 28 Nov 2024 09:13:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tGfGp-00059r-4g for qemu-devel@nongnu.org; Thu, 28 Nov 2024 09:13:27 -0500 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tGfGn-0005wv-GG for qemu-devel@nongnu.org; Thu, 28 Nov 2024 09:13:26 -0500 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-21288402a26so7174465ad.0 for ; Thu, 28 Nov 2024 06:13:25 -0800 (PST) Received: from carbon-x1.. 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Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 +- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 42 ++++++++++++++++++++++++++++++++++----- 3 files changed, 39 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f56ec7c927..1fac03ca99 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -287,7 +287,7 @@ static const char * const riscv_excp_names[] =3D { "load_page_fault", "reserved", "store_page_fault", - "reserved", + "double_trap", "reserved", "reserved", "reserved", diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index dcf63b7f32..ed33610b83 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -706,6 +706,7 @@ typedef enum RISCVException { RISCV_EXCP_INST_PAGE_FAULT =3D 0xc, /* since: priv-1.10.0 */ RISCV_EXCP_LOAD_PAGE_FAULT =3D 0xd, /* since: priv-1.10.0 */ RISCV_EXCP_STORE_PAGE_FAULT =3D 0xf, /* since: priv-1.10.0 */ + RISCV_EXCP_DOUBLE_TRAP =3D 0x10, RISCV_EXCP_SW_CHECK =3D 0x12, /* since: priv-1.13.0 */ RISCV_EXCP_HW_ERR =3D 0x13, /* since: priv-1.13.0 */ RISCV_EXCP_INST_GUEST_PAGE_FAULT =3D 0x14, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 3fabd3379c..0525bfad48 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1848,6 +1848,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool virt =3D env->virt_enabled; bool write_gva =3D false; bool always_storeamo =3D (env->excp_uw2 & RISCV_UW2_ALWAYS_STORE_AMO); + bool vsmode_exc; uint64_t s; int mode; =20 @@ -1862,6 +1863,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) !(env->mip & (1 << cause)); bool vs_injected =3D env->hvip & (1 << cause) & env->hvien && !(env->mip & (1 << cause)); + bool smode_double_trap =3D false; + uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; target_ulong tval =3D 0; target_ulong tinst =3D 0; target_ulong htval =3D 0; @@ -1985,6 +1988,30 @@ void riscv_cpu_do_interrupt(CPUState *cs) mode =3D env->priv <=3D PRV_S && cause < 64 && (((deleg >> cause) & 1) || s_injected || vs_injected) ? PRV_S : PR= V_M; =20 + vsmode_exc =3D env->virt_enabled && (((hdeleg >> cause) & 1) || vs_inj= ected); + /* + * Check double trap condition only if already in S-mode and targeting + * S-mode + */ + if (cpu->cfg.ext_ssdbltrp && env->priv =3D=3D PRV_S && mode =3D=3D PRV= _S) { + bool dte =3D (env->menvcfg & MENVCFG_DTE) !=3D 0; + bool sdt =3D (env->mstatus & MSTATUS_SDT) !=3D 0; + /* In VS or HS */ + if (riscv_has_ext(env, RVH)) { + if (vsmode_exc) { + /* VS -> VS, use henvcfg instead of menvcfg*/ + dte =3D (env->henvcfg & HENVCFG_DTE) !=3D 0; + } else if (env->virt_enabled) { + /* VS -> HS, use mstatus_hs */ + sdt =3D (env->mstatus_hs & MSTATUS_SDT) !=3D 0; + } + } + smode_double_trap =3D dte && sdt; + if (smode_double_trap) { + mode =3D PRV_M; + } + } + if (mode =3D=3D PRV_S) { /* handle the trap in S-mode */ /* save elp status */ @@ -1993,10 +2020,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) } =20 if (riscv_has_ext(env, RVH)) { - uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; - - if (env->virt_enabled && - (((hdeleg >> cause) & 1) || vs_injected)) { + if (vsmode_exc) { /* Trap to VS mode */ /* * See if we need to adjust cause. Yes if its VS mode inte= rrupt @@ -2029,6 +2053,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) s =3D set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); s =3D set_field(s, MSTATUS_SPP, env->priv); s =3D set_field(s, MSTATUS_SIE, 0); + if (riscv_env_smode_dbltrp_enabled(env, virt)) { + s =3D set_field(s, MSTATUS_SDT, 1); + } env->mstatus =3D s; sxlen =3D 16 << riscv_cpu_sxl(env); env->scause =3D cause | ((target_ulong)async << (sxlen - 1)); @@ -2082,9 +2109,14 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mstatus =3D s; mxlen =3D 16 << riscv_cpu_mxl(env); env->mcause =3D cause | ((target_ulong)async << (mxlen - 1)); + if (smode_double_trap) { + env->mtval2 =3D env->mcause; + env->mcause =3D RISCV_EXCP_DOUBLE_TRAP; + } else { + env->mtval2 =3D mtval2; + } env->mepc =3D env->pc; env->mtval =3D tval; - env->mtval2 =3D mtval2; env->mtinst =3D tinst; =20 /* --=20 2.45.2 From nobody Thu Dec 26 21:33:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1732803309; cv=none; d=zohomail.com; s=zohoarc; b=O51oL5tiKdrHtfDB0zKI0/OfssAC0kQwobLi9HTBf2vSUhk/pGPOi0uTVWHO8Xxj66TiRGFxMESfu2VNibXgfUZDb3+shTA1D+LR7/WwbTNap/EUwskXMUivqUwEYK5cxL7QdGHvkLslVinBSbj6fyh6OlNDqOSrlpB7QsGTJYU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1732803309; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=J00ybbkLhRDty+/Gfb3TMi/46nhNnKAwTkyfG+1+1qM=; b=ICT1/BHCa/oON2pUjW6WRtIKnDsUqR6HfBRw35FI9CX5TqluTarHc+TWKC2BZIFYmOnjFDpTIZn+ESxz73kfpFoQ+GPKTjQ3o/fp4HzgGBCdVyLzZgUPvfFLGOpjTtbQkGB60zwCF8daT77bS+zkHffUQmje5IJLSejJMQhpvA4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1732803309724338.9591125035822; Thu, 28 Nov 2024 06:15:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tGfGz-0005Bf-7D; Thu, 28 Nov 2024 09:13:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tGfGw-0005BT-FW for qemu-devel@nongnu.org; Thu, 28 Nov 2024 09:13:34 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tGfGv-0005yO-2h for qemu-devel@nongnu.org; Thu, 28 Nov 2024 09:13:34 -0500 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-21290973bcbso8034015ad.3 for ; Thu, 28 Nov 2024 06:13:32 -0800 (PST) Received: from carbon-x1.. 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Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1fac03ca99..f30630e947 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -192,6 +192,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), + ISA_EXT_DATA_ENTRY(ssdbltrp, PRIV_VERSION_1_13_0, ext_ssdbltrp), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), @@ -1586,6 +1587,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { MULTI_EXT_CFG_BOOL("smrnmi", ext_smrnmi, false), MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), MULTI_EXT_CFG_BOOL("ssaia", ext_ssaia, false), + MULTI_EXT_CFG_BOOL("ssdbltrp", ext_ssdbltrp, false), MULTI_EXT_CFG_BOOL("svade", ext_svade, false), MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true), MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false), --=20 2.45.2 From nobody Thu Dec 26 21:33:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1732803254; cv=none; d=zohomail.com; s=zohoarc; b=mTXuQ/Nn5KwWqi9T6fcttmw6ICbeUNiF0MCMvypOKTSJypraiPneAnQFiBBELbLrGyWYkPi3RKoz0TCYEsvqLsE9t+7sCk+k4lyJ0T3vDb8nsjTQvE2iEdEdvnB582QW3weELhWi+71UFwbrJyMXG4jAF1y5pawN9wkl/LBcAug= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1732803254; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0jQmZHVZGJH8bUITrZGLb9vyQJRHYXGRdZuUVz+4EJM=; b=TDXDI2JZPq5PgqLvxLv79Yu0o7jOMKfP3skdW+4MdU/UUCC5vnM8Vv5EhZgAITDI2i1Mgiza0si604FPIpy7G9pHpYg/yKAkZA9yHtSc4wDKScf6QThUR9m0IPeFYueTUgkkLQcJBIONM0Xn3h/eP8Z+09qAj7MM32uN9hecb+4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1732803254577569.8491238475459; Thu, 28 Nov 2024 06:14:14 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tGfHB-0005RF-A1; Thu, 28 Nov 2024 09:13:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tGfH6-0005QL-6S for qemu-devel@nongnu.org; Thu, 28 Nov 2024 09:13:45 -0500 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tGfH2-00061e-Rq for qemu-devel@nongnu.org; Thu, 28 Nov 2024 09:13:42 -0500 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-2120f9ec28eso7096965ad.1 for ; Thu, 28 Nov 2024 06:13:40 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-215218f452csm13829005ad.48.2024.11.28.06.13.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 06:13:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1732803219; x=1733408019; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0jQmZHVZGJH8bUITrZGLb9vyQJRHYXGRdZuUVz+4EJM=; b=RYxsWi19IojJJsvfNYjKxwVqJMHYhv58DgNg0JUbTUnlk/rG6307ZfULTK33YzhYWo PgXBK9Q9YZpByTdy2FK19fRzB/Il/6IC85Gqf1Evc27KVHq4nVAjNpDo9V94jAHizwvm xDPAw9Jmk7F0suze6F5j05X7hHLNvZYGHI/isXUHj50Yodz1TLdAFAkXD7d3+oyX3zcm 5Y8ygjqBoEFxHkj9JILSuo4ew4NwexQPaMerX6PhmWv5ZdkxlvI1HkDREjlQJs9tZm4W d34Dgnh+pBI9qzOXQ8lxuS4AMayC3ujAhwJNwtbFp3CBHtksr7X0EVLOreGDdgMUkFX3 eTZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732803219; x=1733408019; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0jQmZHVZGJH8bUITrZGLb9vyQJRHYXGRdZuUVz+4EJM=; b=XBza5SIoVOZebXvAKlMbhDqguAeGSXxH6IbW5+nhVsqGwxvGvqzEprFCWQf68yZAhd HnAoVj3wDR9w0gU4sGaNe4gAW+TS8fxGQyFjc08sYit047htLQ/U10efKD68NIvqIQhO aANsyVfNEQovgiwMTfO/ZEQbsGz1QqfVQXkBLIoeAMSLvn+TBKl6rrbfb1KanwB3Mflx jYD1WjDbyz8ngbKTyRFYG2143Tzhl5ww7DkssQ6G+mqY8zdIRp0F63ZriTMVbLMH84lq 8URzjz4zAx7QMhYrdq7IlBGK7GsOTCiwig+mhM3LVN/iTkxs7ICN4rdbCOMny3uenOTc M6/A== X-Forwarded-Encrypted: i=1; AJvYcCUuzAxrX7qznZABXUOSisCFQBLuK77sQdXABS5By9V8wKZbZ89AGSWo01s1ka50OZMbJu3X1GQtjg98@nongnu.org X-Gm-Message-State: AOJu0YxZKPHF2+5WZxrRWmCTPOGxrc/WoofC4U33g7qW+trGOMQ2VTbE jE6zMeflc4iR2L19kWymj4n1/dVIFr+RA3OiqfecZGJ0vTaOgU6fNLB5mvUH9yE= X-Gm-Gg: ASbGncvDVpIjujkIUA1p6+lkGEgYiU2RT+RRefnK30f549GHcP8cZ3OIIBiK2KNqK8O AcVqcWuKHgEs1Cf80GyuMtTtcyNoyN82T+GyULPYgd0bcM8vX/ra4aE7y7iZr3EOiLEL8fwUsOV YFdbvhFGDrDj1DuSqwlfbWWYbK5a7/FT9PztT6LCSL5dC8gTW7n5JuZdJxAvlsCx8aJSB9yMttK kQJ8lVEJCxzN0oAZLErcwbAUtJsAtCafr8RRo6MwDs9WQnMAfg= X-Google-Smtp-Source: AGHT+IEkX3KMCtHfmsbAFe2ylla4UOAbvh+ROmASYv+JpYewu+jeSYrOoe+VyrZLAWeFYzAIYNXNOg== X-Received: by 2002:a17:902:e809:b0:20c:7196:a1e9 with SMTP id d9443c01a7336-2151d32eafbmr52108815ad.13.1732803219140; Thu, 28 Nov 2024 06:13:39 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ved Shanbhogue , Atish Patra , qemu-devel@nongnu.org, Frank Chang Subject: [PATCH v6 6/9] target/riscv: Add Smdbltrp CSRs handling Date: Thu, 28 Nov 2024 15:12:26 +0100 Message-ID: <20241128141230.284320-7-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241128141230.284320-1-cleger@rivosinc.com> References: <20241128141230.284320-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=cleger@rivosinc.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1732803256377019100 Add `ext_smdbltrp`in RISCVCPUConfig and implement MSTATUS.MDT behavior. Also set MDT to 1 at reset according to the specification. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 +++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_cfg.h | 1 + target/riscv/csr.c | 13 +++++++++++++ 4 files changed, 18 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f30630e947..be7c0475bf 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1027,6 +1027,9 @@ static void riscv_cpu_reset_hold(Object *obj, ResetTy= pe type) env->mstatus_hs =3D set_field(env->mstatus_hs, MSTATUS64_UXL, env->misa_mxl); } + if (riscv_cpu_cfg(env)->ext_smdbltrp) { + env->mstatus =3D set_field(env->mstatus, MSTATUS_MDT, 1); + } } env->mcause =3D 0; env->miclaim =3D MIP_SGEIP; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index ed33610b83..ab9d0b19d8 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -566,6 +566,7 @@ #define MSTATUS_MPELP 0x020000000000 /* zicfilp */ #define MSTATUS_GVA 0x4000000000ULL #define MSTATUS_MPV 0x8000000000ULL +#define MSTATUS_MDT 0x40000000000ULL /* Smdbltrp extension */ =20 #define MSTATUS64_UXL 0x0000000300000000ULL #define MSTATUS64_SXL 0x0000000C00000000ULL diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 1194dfd3bc..6699e134ee 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -80,6 +80,7 @@ struct RISCVCPUConfig { bool ext_sstc; bool ext_smcntrpmf; bool ext_ssdbltrp; + bool ext_smdbltrp; bool ext_svadu; bool ext_svinval; bool ext_svnapot; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 611f44e044..055b19d517 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1649,6 +1649,13 @@ static RISCVException write_mstatus(CPURISCVState *e= nv, int csrno, } } =20 + if (riscv_cpu_cfg(env)->ext_smdbltrp) { + mask |=3D MSTATUS_MDT; + if ((val & MSTATUS_MDT) !=3D 0) { + val &=3D ~MSTATUS_MIE; + } + } + if (xl !=3D MXL_RV32 || env->debugger) { if (riscv_has_ext(env, RVH)) { mask |=3D MSTATUS_MPV | MSTATUS_GVA; @@ -1692,6 +1699,12 @@ static RISCVException write_mstatush(CPURISCVState *= env, int csrno, uint64_t valh =3D (uint64_t)val << 32; uint64_t mask =3D riscv_has_ext(env, RVH) ? MSTATUS_MPV | MSTATUS_GVA = : 0; =20 + if (riscv_cpu_cfg(env)->ext_smdbltrp) { + mask |=3D MSTATUS_MDT; + if ((valh & MSTATUS_MDT) !=3D 0) { + mask |=3D MSTATUS_MIE; + } + } env->mstatus =3D (env->mstatus & ~mask) | (valh & mask); =20 return RISCV_EXCP_NONE; --=20 2.45.2 From nobody Thu Dec 26 21:33:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1732803356; cv=none; d=zohomail.com; s=zohoarc; b=AkVWXpVd9nvFE1t8mKNsFz9y2wj0JRy9PVSzl8mHYoNV3K5XxpNXCk3dS8S9MgIrAypW+AA3cJ2C7JaPTYJ9icoWUfDL+XH7WAZ46koNYobFu5bkWb+WL/4G0IbRr9uqQs9ZuPT3YeKOHdgNJVnj+SsQvmsYt0r33MF0NZ4CrtQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1732803356; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=xOP7Hqao7kiNDStvwCeVXCCvUD1H/qgyxYLIdZ3OWV8=; b=OruhDC9zLMkMMuU0ve0mhc7csVb46B+Ucnl+jPoZVUmiVa/Dx72NiEFmVU8spMNTQJTvegI5pD7Vfns2HDWzBBvzHwS0Z/jDqm3EehQ/fSotRPeIEmmpZWKZ/WbrzfxAWIBh9QKxMiQUxUvLZyfWkHgn400b6GmtxilkA8Tv7k8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 173280335661817.216633841664816; Thu, 28 Nov 2024 06:15:56 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tGfHO-0005jm-8Z; Thu, 28 Nov 2024 09:14:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tGfHD-0005Ul-KV for qemu-devel@nongnu.org; Thu, 28 Nov 2024 09:13:53 -0500 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tGfHA-00063k-0v for qemu-devel@nongnu.org; Thu, 28 Nov 2024 09:13:50 -0500 Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-7252b7326f4so820875b3a.2 for ; Thu, 28 Nov 2024 06:13:47 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-215218f452csm13829005ad.48.2024.11.28.06.13.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 06:13:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1732803226; x=1733408026; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xOP7Hqao7kiNDStvwCeVXCCvUD1H/qgyxYLIdZ3OWV8=; b=2yPQ4CmvBM3nUIDIpNyBktjXHZZt0zJR6KItmBsGPlEwzdKXlAp8r0DEc7tBAQGTmD hsmE9TLUHgKK6QomY+I/TxwjyLHKEhiaXiuO2tNChd+TQxAj9KNJxD8FDRhYzSiZBfFg GnQgs4Fvrh7M3E2m0LjvoScjFtx6TYGO5LHXWKZQU4c3Ev4UebcsPlItz+Cn08ZFyFS+ Dp56VOSZQAIawHhx36jeK1VKiFQM4ALCaCaxoI+YgUJmgybn8i3hZZ4o8/ix4O35v9t3 Oj009XU4XSlI6c7FamRQ4puflXa++6jZNMoiwfH25HsHiC8dfUrXA3rs3q5bTPCZ1T5o sGlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732803226; x=1733408026; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xOP7Hqao7kiNDStvwCeVXCCvUD1H/qgyxYLIdZ3OWV8=; b=OVlASOTOdt27Y4ygZiz/4kymFh++QBvs+REl6KROBWmFM/LwViSJ2D2nd9X9Ts+tWw Uu9fjXUQOoUL+T7CpzMazB0zhYFxq0CNOYqjbFmHs59N7Ksj+4HdsjTtPTAJm5nMA3AJ esqMvYxOGW1P43BNHy/UODNguU7wmHF9MeUEQuSPWcxoDrdV+3ndkTZG9o5wrcCcCND3 2vzMkKHldhs1p44eEXqx4kwwvhziEV7AlyEXvZ/IWeUCEi5n/1s5FKGkP1vdItpQWNDS P7tsRbF1AfcwJGzzmHZ63R4w9kC6AR5xV0sl40DrOu0876Q4eOT+LzuubIsyZ9/XKjef +Z/Q== X-Forwarded-Encrypted: i=1; AJvYcCWN+o906wLPUmhk1BPiOaA1A4ekDtI6ZkDRirvz7mJ6gDaekxstRc00s8756mfOok39UIEEOc+fFp7b@nongnu.org X-Gm-Message-State: AOJu0YzO10IuF5c4NtorZk+7Mckoi2FCJf93gFW/K+tGX3q/l2fIxzZB 8tPyWjD2s+26jK6s6nAgP+Bp0uaZ9UZ86koELQ+5UxdJ8EV+55XgUfLkVg5OmlU= X-Gm-Gg: ASbGncsEPbOR4NonJuoZOCV55g5OuATwTdc1/Vvh+wbs7mWg2AP0ZuYoiVl0M/n/FkE DFBEMuqv6XghZS7OXFjKrCIGoi6oXDVdya+LpRvqp1Msl+lkREb3t07saWWrT6t08qBh8rSYyGN JkpiiB3WeOuSGUrWpdwKcEE1ogSioEkBeQc0uXFz+s6JkCXMooa5aeK/R3Sa0DwVWGX6MGe/4a0 9gYrAMoYF2BA5oZGvzkmyiZLgxmeDj/SzBps97CDp1Gy7y7Row= X-Google-Smtp-Source: AGHT+IGpSoh0+KuaUmbtzf7psTJL2sEZHjOMJGTPxqPhdzCChYmOavow3xeHBSZMOHxavsOGbeO9Tg== X-Received: by 2002:a17:902:f64c:b0:20b:7210:5859 with SMTP id d9443c01a7336-21501d587d8mr96068425ad.38.1732803226644; Thu, 28 Nov 2024 06:13:46 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ved Shanbhogue , Atish Patra , qemu-devel@nongnu.org, Frank Chang Subject: [PATCH v6 7/9] target/riscv: Implement Smdbltrp sret, mret and mnret behavior Date: Thu, 28 Nov 2024 15:12:27 +0100 Message-ID: <20241128141230.284320-8-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241128141230.284320-1-cleger@rivosinc.com> References: <20241128141230.284320-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=cleger@rivosinc.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1732803356910019100 When the Ssdbltrp extension is enabled, SSTATUS.MDT field is cleared when executing sret if executed in M-mode. When executing mret/mnret, SSTATUS.MDT is cleared. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Alistair Francis --- target/riscv/op_helper.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index eeacb2d1a1..9de4df207c 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -299,6 +299,9 @@ target_ulong helper_sret(CPURISCVState *env) } mstatus =3D set_field(mstatus, MSTATUS_SDT, 0); } + if (riscv_cpu_cfg(env)->ext_smdbltrp && env->priv >=3D PRV_M) { + mstatus =3D set_field(mstatus, MSTATUS_MDT, 0); + } if (env->priv_ver >=3D PRIV_VERSION_1_12_0) { mstatus =3D set_field(mstatus, MSTATUS_MPRV, 0); } @@ -384,6 +387,9 @@ target_ulong helper_mret(CPURISCVState *env) if (riscv_cpu_cfg(env)->ext_ssdbltrp) { mstatus =3D ssdbltrp_mxret(env, mstatus, prev_priv, prev_virt); } + if (riscv_cpu_cfg(env)->ext_smdbltrp) { + mstatus =3D set_field(mstatus, MSTATUS_MDT, 0); + } if ((env->priv_ver >=3D PRIV_VERSION_1_12_0) && (prev_priv !=3D PRV_M)= ) { mstatus =3D set_field(mstatus, MSTATUS_MPRV, 0); } @@ -429,6 +435,12 @@ target_ulong helper_mnret(CPURISCVState *env) env->mstatus =3D ssdbltrp_mxret(env, env->mstatus, prev_priv, prev= _virt); } =20 + if (riscv_cpu_cfg(env)->ext_smdbltrp) { + if (prev_priv < PRV_M) { + env->mstatus =3D set_field(env->mstatus, MSTATUS_MDT, 0); + } + } + if (riscv_has_ext(env, RVH) && prev_virt) { riscv_cpu_swap_hypervisor_regs(env); } --=20 2.45.2 From nobody Thu Dec 26 21:33:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1732803336; cv=none; d=zohomail.com; s=zohoarc; b=aHyxiWyoLPvdDiT82hBQt7xr+tXNpQRWVAhFMGQx3IY5VJY3Cj6FGHMnmQgOuPFrkg5wVYqIDAP+vcgTrOpBctJTPPuQaH5SN3F3N1mxM0sWEJ7PH7rZqHW1+6qtjX5PuRX509hZl+Dudx84jDiRzU9W6C+UJ1oc8hfUESC2m2k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1732803336; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=6Nv58FYpnM7owBpC7KsSmszH2TLrrLmHRGoBsSTg858=; b=RRvqQQaP97zUXBPWuNwL1dR9nkIIMOEv9jCLigGvBCyLERVOvq3BKa1USmp8MIE5jqsI4ARMtZ60Vu4JZs78LNEKKJhs17GNisd7MPUirm6lWlsaQLfyzdtDWD1eeI5R6E6qs9Oy+zPdTdaWFPw3k5DB2R8AIRO5IJbZS8s70so= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1732803336213987.6826422312419; Thu, 28 Nov 2024 06:15:36 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tGfHQ-0005vf-LU; Thu, 28 Nov 2024 09:14:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tGfHL-0005dl-4e for qemu-devel@nongnu.org; Thu, 28 Nov 2024 09:13:59 -0500 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tGfHH-000669-JM for qemu-devel@nongnu.org; Thu, 28 Nov 2024 09:13:57 -0500 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-724d8422f37so804067b3a.2 for ; Thu, 28 Nov 2024 06:13:55 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-215218f452csm13829005ad.48.2024.11.28.06.13.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 06:13:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1732803234; x=1733408034; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6Nv58FYpnM7owBpC7KsSmszH2TLrrLmHRGoBsSTg858=; b=1xyLNQIlqMre0v5m1LxLF+vUs2ANCuCw3sGCJi6jz/IzE67+O8Ugj6gGyVrx85hEaw QFQPHE11E4uUwXXfFE6JforaNNzjS4U0esbWof13dmzediWPPXbdJyhPOgfPrbmAt6nf t6akI96yRJQ7hh24Z5MYkSecxAa8W/iFA6toaGmJtQHbTyVCbs143AcpuuFfAx7fCi2T Ukr8MZJqmjuPm2dzjSclRpUeCHUIvvEvS0xkaPCeR0nnIF257zPdKug2YjSFytaQTGa1 s+pDpyG3GLEmpOZ2zoifKbxJgl3pq4D09wOtJ4rxqVj+0S7PaheuL/PVVIYnLI1k/F/a fGrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732803234; x=1733408034; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6Nv58FYpnM7owBpC7KsSmszH2TLrrLmHRGoBsSTg858=; b=VaTAwXV25KtMvgJRIwcbnYkCitzBDfvCOLLiG6MXU2RNV1JVoy3Rb+Hl1auJzZN9/O ldByeDC7FyUDunLJIj8B98XeRptnA3CRT46fSmvGpmsyLxtnzmdr4WLM3Jnl27BsCpHH JBt5wpDXsNgMP7k5q1PI9C5svLRTqnBYnoyFQ0nSAFffSAVOIGCvUgmRQ9x4Y/ImCX+9 m5qnZisemPFF7F9lO9egeiD2KgLzSzsiu68kxdKzzmrKcCRcK02TaWwa7NXwowI+wIsT dkAuVO7ftSjLDKVBmPvViziUjyuo5FVHvgE5nhtHaD0X2Aljp2VPuznNg8gZeATfrLHk LdwQ== X-Forwarded-Encrypted: i=1; AJvYcCU9KAMBnRKDKj5Tw47PTwzMvnqV+uNCzA/ZbAsKprolnRJunAH6kvKv4hEhkNYtgrW1Py72tLdaX/NB@nongnu.org X-Gm-Message-State: AOJu0Yzhm6b8Jjf1KB8frCMtY+khs8wmHE83EtmvCs7h6NQ8UCU+bTds nMXgTLgWGSR8MuzaR4+Nmb3GSMiEwUI6VvlzhBEtuJgTE1p6tRLdoipVlTAsjd8= X-Gm-Gg: ASbGncus5ittUNRZdE6Gq12kHcIILd0hzvymM1FtvgrxMGzvh9ZGFndA5MWGQ0QdPbG lRjPxX+dvP18LFagg/8q7RRZlO+QDDYqJPWgEuUfykXNur+9ot0UWUQ3Cm8sbs+jZw0AKxrfSLm 8/U1mZlxVwZ/GPNmjP1Kv7aXijgzsxzTSwnU+PUc96o2pZmsAivC7uDSUuGdFaTD87nDWtz9VAO P+fzbnZETBI95WoZcoHr2TzQRPd3Fpoh1dzhS4eYB8BvfeSoIE= X-Google-Smtp-Source: AGHT+IEaFeEFh3xOHmzfPqrm/lV9EtxNF4t/TvFa+7dvmIHZuqdpmaKlYGYQ7CRQqbzNjIYM1Z0XhQ== X-Received: by 2002:a17:902:e84a:b0:20c:6b11:deef with SMTP id d9443c01a7336-21501e5c036mr96258615ad.48.1732803234036; Thu, 28 Nov 2024 06:13:54 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ved Shanbhogue , Atish Patra , qemu-devel@nongnu.org, Frank Chang Subject: [PATCH v6 8/9] target/riscv: Implement Smdbltrp behavior Date: Thu, 28 Nov 2024 15:12:28 +0100 Message-ID: <20241128141230.284320-9-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241128141230.284320-1-cleger@rivosinc.com> References: <20241128141230.284320-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=cleger@rivosinc.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1732803336676019100 When the Smsdbltrp ISA extension is enabled, if a trap happens while MSTATUS.MDT is already set, it will trigger an abort or an NMI is the Smrnmi extension is available. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 56 ++++++++++++++++++++++++++++----------- 1 file changed, 40 insertions(+), 16 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 0525bfad48..f46be166f6 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1835,6 +1835,23 @@ static target_ulong promote_load_fault(target_ulong = orig_cause) /* if no promotion, return original cause */ return orig_cause; } + +static void riscv_do_nmi(CPURISCVState *env, target_ulong cause, bool virt) +{ + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_NMIE, false); + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_MNPV, virt); + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_MNPP, env->priv); + env->mncause =3D cause; + env->mnepc =3D env->pc; + env->pc =3D env->rnmi_irqvec; + + if (cpu_get_fcfien(env)) { + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_MNPELP, env->e= lp); + } + + riscv_cpu_set_mode(env, PRV_M, false); +} + /* * Handle Traps * @@ -1874,22 +1891,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool nnmi_excep =3D false; =20 if (cpu->cfg.ext_smrnmi && env->rnmip && async) { - env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_NMIE, false); - env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_MNPV, - env->virt_enabled); - env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_MNPP, - env->priv); - env->mncause =3D cause | ((target_ulong)1U << (TARGET_LONG_BITS - = 1)); - env->mnepc =3D env->pc; - env->pc =3D env->rnmi_irqvec; - - if (cpu_get_fcfien(env)) { - env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_MNPELP, en= v->elp); - } - - /* Trapping to M mode, virt is disabled */ - riscv_cpu_set_mode(env, PRV_M, false); - + riscv_do_nmi(env, cause | ((target_ulong)1U << (TARGET_LONG_BITS -= 1)), + virt); return; } =20 @@ -2101,11 +2104,32 @@ void riscv_cpu_do_interrupt(CPUState *cs) /* Trapping to M mode, virt is disabled */ virt =3D false; } + /* + * If the hart encounters an exception while executing in M-mode, + * with the mnstatus.NMIE bit clear, the program counter is set to + * the RNMI exception trap handler address. + */ + nnmi_excep =3D cpu->cfg.ext_smrnmi && + !get_field(env->mnstatus, MNSTATUS_NMIE) && + !async; =20 s =3D env->mstatus; s =3D set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); s =3D set_field(s, MSTATUS_MPP, env->priv); s =3D set_field(s, MSTATUS_MIE, 0); + if (cpu->cfg.ext_smdbltrp) { + if (env->mstatus & MSTATUS_MDT) { + assert(env->priv =3D=3D PRV_M); + if (!cpu->cfg.ext_smrnmi || nnmi_excep) { + cpu_abort(CPU(cpu), "M-mode double trap\n"); + } else { + riscv_do_nmi(env, cause, false); + return; + } + } + + s =3D set_field(s, MSTATUS_MDT, 1); + } env->mstatus =3D s; mxlen =3D 16 << riscv_cpu_mxl(env); env->mcause =3D cause | ((target_ulong)async << (mxlen - 1)); --=20 2.45.2 From nobody Thu Dec 26 21:33:23 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1732803294; cv=none; d=zohomail.com; s=zohoarc; b=SYfNLyk6pTlTMKZlnkXtYV6FU/3MATpd6eATcb8fe3zp9V/4IksDXdGb0XvoRQOXl+DPIr4oWtJYUwN/RJpNmoB/aGqm5vDXSnypARfExUxFVIIqSNY3alZH5JvbvDj3m1W2dKDC39TlG4bg0KTLl8AdmrGss2ns7HqYuip5IsU= ARC-Message-Signature: i=1; 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Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index be7c0475bf..9e2166a810 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -185,6 +185,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), + ISA_EXT_DATA_ENTRY(smdbltrp, PRIV_VERSION_1_13_0, ext_smdbltrp), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), @@ -1586,6 +1587,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true), =20 MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false), + MULTI_EXT_CFG_BOOL("smdbltrp", ext_smdbltrp, false), MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), MULTI_EXT_CFG_BOOL("smrnmi", ext_smrnmi, false), MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), --=20 2.45.2