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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-385ccd68958sm1292959f8f.67.2024.11.28.02.43.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:43:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732790597; x=1733395397; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4tTkIIhrcxBZurdxQEsXyUswGgpnjQ7q8C2Djt24mE4=; b=r9xj4aTE4ShualRlnld2+iMsZzYiXm2LI8n0CBjxgSoOzLaMS2jcyYMQPRu6rngEa2 dAwR+LeYK7/6PwmdIBuNvutUS1KlCuuzdodyeFww33hKJf4P8fN4dW5EH0q+PBWXlDLj d3VSYbeXyRuF4DlzEwWqVz9Bp2vsfvBTc012EqK01f2iay24ayWUt/Og/ViZdeQiaWq9 +bnWk3U4Uv9W/95ufPXR7GlIdj5z+zJVdrwtUpATDLSkptVBo3h+ritqLEOGpmipAQ8O Txs8DDvF1VKwFORbszyk69r94SjCKkSGllUVaJ7mhqVykVd21PYeKauqcJp/iYH5NiI0 0ojA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732790597; x=1733395397; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4tTkIIhrcxBZurdxQEsXyUswGgpnjQ7q8C2Djt24mE4=; b=Y2YZ0NOSwWGiYCSGSwe+SSnjm1XMjbaqfnDBZjmFG30v+yzIZssIcnBvJ+8uiUu0wV TcbHc1awbdeMSumaivczgI9rx99DHWjGwwR8JOX17BmZ4TQVHRgD0Mge2mtAaYKw2zUY 4Rf21aIVW1wxp8cENgSbEYunbZ0ANae4JvKduR9QTvIrRcr870qPFZalnCuXrf1ULBew 2MusaRTp/0VxUwFdYDBYZ53RR8EhatNwwQx5GB6lcNFat0Y/1++4fIY+hMuouyQAfA8o 2IPPgpGPaqsdLIQpqmEXMlJHMNXwjC4zssD0d8Vm9BvsDjzNI/e/x9BsHgeSSPfdV8VB QcIw== X-Gm-Message-State: AOJu0YxqPS9zo+r2KclTFbuIs8x4kLNggfWLAo+YJCTNN7ttujjYj/Iv Pv8y22u27MBqhBHV4hKfzy4sfcdOWOksQtSvEj5CEH540GiXyd8UzpHglnC02dosIH5s8Y5+SkN + X-Gm-Gg: ASbGncvcXQR4goIlCIN92l986Vwc377byLySDxjSPNsJA2DNULGAmn5lnJGMCL9ofq5 zqp1FtWqvRqvyUiLFuo6zfTFy05P6EKWzocQgVNPKJgMH35xawY16ezpVJch5Jw0v7pwI1up/EJ z+ZYtsSJU13va9wzk96591jobI1FY7Iy0rpDHE9EeXZ35W8r5sytN+K5UCbZRE5qU/qd3LGn8GG 9Ta1D6DGlOQrPtKdsbH0dnRAs5So4rjcBANKcc9SYHvueK0BQgykzU= X-Google-Smtp-Source: AGHT+IG5lSeN2KFb6Yig+OEBeyIMwuYEw2rT4BgFuZynv+ZIVjSU7aBGEarxaDG3Yeq6RQ+0eWBgGw== X-Received: by 2002:a05:6000:2b0f:b0:382:4a75:57f4 with SMTP id ffacd0b85a97d-385c6ef38bdmr3968690f8f.56.1732790597461; Thu, 28 Nov 2024 02:43:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Song Gao , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo , Nicholas Piggin , Daniel Henrique Barboza , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Max Filippov Subject: [PATCH for-10.0 05/25] target/arm: Set FloatInfZeroNaNRule explicitly Date: Thu, 28 Nov 2024 10:42:50 +0000 Message-Id: <20241128104310.3452934-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241128104310.3452934-1-peter.maydell@linaro.org> References: <20241128104310.3452934-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1732790679472019100 Content-Type: text/plain; charset="utf-8" Set the FloatInfZeroNaNRule explicitly for the Arm target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.c | 3 +++ fpu/softfloat-specialize.c.inc | 8 +------- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6938161b954..ead39793985 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -173,11 +173,14 @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELCh= angeHookFn *hook, * * tininess-before-rounding * * 2-input NaN propagation prefers SNaN over QNaN, and then * operand A over operand B (see FPProcessNaNs() pseudocode) + * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet, + * and the input NaN if it is signalling */ static void arm_set_default_fp_behaviours(float_status *s) { set_float_detect_tininess(float_tininess_before_rounding, s); set_float_2nan_prop_rule(float_2nan_prop_s_ab, s); + set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s); } =20 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index f5b422e07b5..b3ffa54f368 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -489,13 +489,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass = b_cls, FloatClass c_cls, /* * Temporarily fall back to ifdef ladder */ -#if defined(TARGET_ARM) - /* - * For ARM, the (inf,zero,qnan) case returns the default NaN, - * but (inf,zero,snan) returns the input NaN. - */ - rule =3D float_infzeronan_dnan_if_qnan; -#elif defined(TARGET_MIPS) +#if defined(TARGET_MIPS) if (snan_bit_is_one(status)) { /* * For MIPS systems that conform to IEEE754-1985, the (inf,zer= o,nan) --=20 2.34.1