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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434b0f7150esm17596885e9.42.2024.11.28.02.38.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 02:38:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732790313; x=1733395113; darn=nongnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=TP0Ip4Rzdbzg4KxmAGds5CRnBSGPx3UMLoPkVjTmsAI=; b=mVjTVCco0qoj+Rters8+MNObTJTN5QUR5QTMhWzzxytWe523OI5y25yciNtDwMEtMb YnCDf6VzUSdviSiatlsDElHeJbHkOtBcjt52hz6tCZWmaeL8FUYW3y2NngMPTWJXrA9z bNtCUirUbF4Cr04ra6qw33BzJP9B656QLdWfTLloEy//aBMjIKuZgjiwEeTbifl0v89e A+oGcV/hQE7kPAfpQhEwROpDJvHA15rB0T5U8c39ZBHlUVbPAyXZ9iVyVujIN/ZsHmez 3NxnLYxlXA3sEOkbJCEgTxG7IGU/a/6mLybhHPKTn7IpLgQv9iN/CdXCJK8pK7dBLAKL SfJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732790313; x=1733395113; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=TP0Ip4Rzdbzg4KxmAGds5CRnBSGPx3UMLoPkVjTmsAI=; b=bdvGLCOiUkZ73sIbkiSRW3MSPz0WQIrBB+zFXD31exHf8lKzpqEHEVTYe7GbZMK5Y0 IYTB1NaL08uiyn/8p6jNQAsSUY9DjDsu5jr67aoiMMhdvi47MhTKSBUKPmuSnQl1Py7o ZO6qZf7Kxd6ugqwPf1ZH1NOswMefbKYab1ICNpEs+VZjJdBDH06eW8G39etUsnKXF5NC I9ZGAF01+KIj4DrDaSgujBoRxyNQkodc1+a6aRVIxrF80+MXTpk5URw7VM9OX3wPyS7C 6P0ND5DPfhzgzD7lf4k0rGaB9LVSOwD9tBawRMOdomJT5gkRxmxswrxag6AK+ZFLMaFY kfSQ== X-Gm-Message-State: AOJu0YxdrrUGt2Mitpzdc/2tngxsnQ/Gw4FanIQeqWjHXWGH+WgV+lRA DRxOn0zZeBphuI4Omx0ZoRsXsDysKBTUX/+3o29NL9odC4L3SSPFQM8v56/EkpxCNmT3/fqxn+m u X-Gm-Gg: ASbGncuo6cSTKoR+ikHv1Hnj9DCdP0WDlIDIs7ezHeCd7Y7DWsLg0cZnDwg66vowjeC FLZZCAx0fpOPMPGY/yOvhgS7Ew1FVUNZJXztcw98+scsnxuWzaC6c3UaTyz+S7zP/JFcZ5CvosO J8NkAjtzzjjtaQmxOWA30nPsHlj60ZiDPF+Tvs4PSfigS9bwBDrrD8Yj2P1lKLaig80pQTyRhQx USvu6dQDQLPHHMJJyBKV50eYh1f216iwuVyKFpad/1vSxPiW/dPedx/ X-Google-Smtp-Source: AGHT+IGA3jW6Edqm5aXqMBYN81KhO8fM4qovl5967vXF+a0VgzWNLA09gieyGZf4xCYdyCfEzHPx3A== X-Received: by 2002:a05:600c:458d:b0:433:c463:62dd with SMTP id 5b1f17b1804b1-434a9e0e5femr57951435e9.27.1732790313384; Thu, 28 Nov 2024 02:38:33 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org Subject: [PATCH for-9.2] target/riscv: Avoid bad shift in riscv_cpu_do_interrupt() Date: Thu, 28 Nov 2024 10:38:31 +0000 Message-Id: <20241128103831.3452572-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1732790368005019100 Content-Type: text/plain; charset="utf-8" In riscv_cpu_do_interrupt() we use the 'cause' value we got out of cs->exception as a shift value. However this value can be larger than 31, which means that "1 << cause" is undefined behaviour, because we do the shift on an 'int' type. This causes the undefined behaviour sanitizer to complain on one of the check-tcg tests: $ UBSAN_OPTIONS=3Dprint_stacktrace=3D1:abort_on_error=3D1:halt_on_error=3D1= ./build/clang/qemu-system-riscv64 -M virt -semihosting -display none -devi= ce loader,file=3Dbuild/clang/tests/tcg/riscv64-softmmu/issue1060 ../../target/riscv/cpu_helper.c:1805:38: runtime error: shift exponent 63 i= s too large for 32-bit type 'int' #0 0x55f2dc026703 in riscv_cpu_do_interrupt /mnt/nvmedisk/linaro/qemu-f= rom-laptop/qemu/build/clang/../../target/riscv/cpu_helper.c:1805:38 #1 0x55f2dc3d170e in cpu_handle_exception /mnt/nvmedisk/linaro/qemu-fro= m-laptop/qemu/build/clang/../../accel/tcg/cpu-exec.c:752:9 In this case cause is RISCV_EXCP_SEMIHOST, which is 0x3f. Use 1ULL instead to ensure that the shift is in range. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson --- target/riscv/cpu_helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 0a3ead69eab..45806f5ab0f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1802,10 +1802,10 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool async =3D !!(cs->exception_index & RISCV_EXCP_INT_FLAG); target_ulong cause =3D cs->exception_index & RISCV_EXCP_INT_MASK; uint64_t deleg =3D async ? env->mideleg : env->medeleg; - bool s_injected =3D env->mvip & (1 << cause) & env->mvien && - !(env->mip & (1 << cause)); - bool vs_injected =3D env->hvip & (1 << cause) & env->hvien && - !(env->mip & (1 << cause)); + bool s_injected =3D env->mvip & (1ULL << cause) & env->mvien && + !(env->mip & (1ULL << cause)); + bool vs_injected =3D env->hvip & (1ULL << cause) & env->hvien && + !(env->mip & (1ULL << cause)); target_ulong tval =3D 0; target_ulong tinst =3D 0; target_ulong htval =3D 0; --=20 2.34.1