From nobody Fri Dec 27 07:05:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1732759907660782.9750019944314; Wed, 27 Nov 2024 18:11:47 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tGTzI-0005k4-N3; Wed, 27 Nov 2024 21:10:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tGTzG-0005jC-Pk for qemu-devel@nongnu.org; Wed, 27 Nov 2024 21:10:34 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tGTzC-0006v9-6X for qemu-devel@nongnu.org; Wed, 27 Nov 2024 21:10:34 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8DxL60S0UdnHFRKAA--.40553S3; Thu, 28 Nov 2024 10:10:26 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMCxNMAQ0UdnfNJqAA--.46399S5; Thu, 28 Nov 2024 10:10:25 +0800 (CST) From: Bibo Mao To: Song Gao , Huacai Chen Cc: Jiaxun Yang , Igor Mammedov , qemu-devel@nongnu.org Subject: [PATCH 3/5] hw/intc/loongarch_ipi: Add cpu map table from physical cpu id Date: Thu, 28 Nov 2024 10:10:22 +0800 Message-Id: <20241128021024.662057-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20241128021024.662057-1-maobibo@loongson.cn> References: <20241128021024.662057-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMCxNMAQ0UdnfNJqAA--.46399S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1732759908755019100 Content-Type: text/plain; charset="utf-8" Bitmap table present_cpu_map is added, it is to allocate logical cpu when CPU object is created. Also present_cpu array is added to get logical cpu from physical cpu id. Signed-off-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 24 ++++++++++++++++++++++++ include/hw/intc/loongarch_ipi.h | 6 ++++++ include/hw/loongarch/virt.h | 9 +++++++++ 3 files changed, 39 insertions(+) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index 7ea65bcef3..9296006cf6 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -8,6 +8,7 @@ #include "qemu/osdep.h" #include "hw/boards.h" #include "qemu/error-report.h" +#include "qapi/error.h" #include "hw/intc/loongarch_ipi.h" #include "target/loongarch/cpu.h" =20 @@ -85,11 +86,33 @@ static void loongarch_cpu_unplug(HotplugHandler *hotplu= g_dev, } } =20 +static void loongarch_ipi_realize(DeviceState *dev, Error **errp) +{ + LoongarchIPIState *lis =3D LOONGARCH_IPI(dev); + LoongarchIPIClass *lic =3D LOONGARCH_IPI_GET_CLASS(dev); + Error *local_err =3D NULL; + int i; + + lic->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + for (i =3D 0; i < MAX_PHY_ID; i++) { + lis->present_cpu[i] =3D INVALID_CPU; + } +} + static void loongarch_ipi_class_init(ObjectClass *klass, void *data) { + DeviceClass *dc =3D DEVICE_CLASS(klass); LoongsonIPICommonClass *licc =3D LOONGSON_IPI_COMMON_CLASS(klass); + LoongarchIPIClass *lic =3D LOONGARCH_IPI_CLASS(klass); HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(klass); =20 + device_class_set_parent_realize(dc, loongarch_ipi_realize, + &lic->parent_realize); licc->get_iocsr_as =3D get_iocsr_as; licc->cpu_by_arch_id =3D loongarch_cpu_by_arch_id; hc->plug =3D loongarch_cpu_plug; @@ -100,6 +123,7 @@ static const TypeInfo loongarch_ipi_types[] =3D { { .name =3D TYPE_LOONGARCH_IPI, .parent =3D TYPE_LOONGSON_IPI_COMMON, + .instance_size =3D sizeof(LoongarchIPIState), .class_init =3D loongarch_ipi_class_init, .interfaces =3D (InterfaceInfo[]) { { TYPE_HOTPLUG_HANDLER }, diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ip= i.h index 276b3040a3..1ef64af85c 100644 --- a/include/hw/intc/loongarch_ipi.h +++ b/include/hw/intc/loongarch_ipi.h @@ -10,16 +10,22 @@ =20 #include "qom/object.h" #include "hw/intc/loongson_ipi_common.h" +#include "hw/loongarch/virt.h" =20 +#define INVALID_CPU -1 #define TYPE_LOONGARCH_IPI "loongarch_ipi" OBJECT_DECLARE_TYPE(LoongarchIPIState, LoongarchIPIClass, LOONGARCH_IPI) =20 struct LoongarchIPIState { LoongsonIPICommonState parent_obj; + DECLARE_BITMAP(present_cpu_map, LOONGARCH_MAX_CPUS); + int present_cpu[MAX_PHY_ID]; + CPUState *cs[MAX_PHY_ID]; }; =20 struct LoongarchIPIClass { LoongsonIPICommonClass parent_class; + DeviceRealize parent_realize; }; =20 #endif diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index 9ba47793ef..7754c85f0b 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -14,6 +14,15 @@ #include "hw/loongarch/boot.h" =20 #define LOONGARCH_MAX_CPUS 256 +/* + * LoongArch Reference Manual Vol1, Chapter 7.4.12 CPU Identity + * For CPU architecture, bit0 .. bit8 is valid for CPU id, max cpuid is 5= 12 + * However for IPI/Eiointc interrupt controller, max supported cpu id for + * irq routing is 256 + * + * Here max cpu id is 256 for virt machine + */ +#define MAX_PHY_ID 0x100 =20 #define VIRT_FWCFG_BASE 0x1e020000UL #define VIRT_BIOS_BASE 0x1c000000UL --=20 2.39.3