From nobody Fri Dec 27 06:04:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1732759926145124.34053336055672; Wed, 27 Nov 2024 18:12:06 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tGTzK-0005kU-Bu; Wed, 27 Nov 2024 21:10:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tGTzG-0005jA-PU for qemu-devel@nongnu.org; Wed, 27 Nov 2024 21:10:34 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tGTzB-0006v8-W7 for qemu-devel@nongnu.org; Wed, 27 Nov 2024 21:10:34 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxieAR0UdnFFRKAA--.13853S3; Thu, 28 Nov 2024 10:10:25 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMCxNMAQ0UdnfNJqAA--.46399S3; Thu, 28 Nov 2024 10:10:24 +0800 (CST) From: Bibo Mao To: Song Gao , Huacai Chen Cc: Jiaxun Yang , Igor Mammedov , qemu-devel@nongnu.org Subject: [PATCH 1/5] hw/intc/loongson_ipi: Add more output parameter for cpu_by_arch_id Date: Thu, 28 Nov 2024 10:10:20 +0800 Message-Id: <20241128021024.662057-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20241128021024.662057-1-maobibo@loongson.cn> References: <20241128021024.662057-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMCxNMAQ0UdnfNJqAA--.46399S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1732759926843019100 Content-Type: text/plain; charset="utf-8" Add logic cpu index output parameter for function cpu_by_arch_id, CPUState::cpu_index is logic cpu slot index for possible_cpus. However it is logic cpu index with LoongsonIPICommonState::IPICore, here hide access for CPUState::cpu_index directly, it comes from function cpu_by_arch_id(). Signed-off-by: Bibo Mao --- hw/intc/loongarch_ipi.c | 19 +++++++++++++++---- hw/intc/loongson_ipi.c | 23 ++++++++++++++++++++++- hw/intc/loongson_ipi_common.c | 21 ++++++++++++--------- include/hw/intc/loongson_ipi_common.h | 3 ++- 4 files changed, 51 insertions(+), 15 deletions(-) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index 2ae1a42c46..c5ecd68952 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -36,17 +36,28 @@ static CPUArchId *find_cpu_by_archid(MachineState *ms, = uint32_t id) return found_cpu; } =20 -static CPUState *loongarch_cpu_by_arch_id(int64_t arch_id) +static int loongarch_cpu_by_arch_id(LoongsonIPICommonState *lics, + int64_t arch_id, int *index, CPUState = **pcs) { MachineState *machine =3D MACHINE(qdev_get_machine()); CPUArchId *archid; + CPUState *cs; =20 archid =3D find_cpu_by_archid(machine, arch_id); - if (archid) { - return CPU(archid->cpu); + if (archid && archid->cpu) { + cs =3D archid->cpu; + if (index) { + *index =3D cs->cpu_index; + } + + if (pcs) { + *pcs =3D cs; + } + + return MEMTX_OK; } =20 - return NULL; + return MEMTX_ERROR; } =20 static void loongarch_ipi_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 4e08f03510..885916e9cd 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -19,6 +19,27 @@ static AddressSpace *get_iocsr_as(CPUState *cpu) return NULL; } =20 +static int loongson_cpu_by_arch_id(LoongsonIPICommonState *lics, + int64_t arch_id, int *index, CPUState *= *pcs) +{ + CPUState *cs; + + cs =3D cpu_by_arch_id(arch_id); + if (cs =3D=3D NULL) { + return MEMTX_ERROR; + } + + if (index) { + *index =3D cs->cpu_index; + } + + if (pcs) { + *pcs =3D cs; + } + + return MEMTX_OK; +} + static const MemoryRegionOps loongson_ipi_core_ops =3D { .read_with_attrs =3D loongson_ipi_core_readl, .write_with_attrs =3D loongson_ipi_core_writel, @@ -74,7 +95,7 @@ static void loongson_ipi_class_init(ObjectClass *klass, v= oid *data) device_class_set_parent_unrealize(dc, loongson_ipi_unrealize, &lic->parent_unrealize); licc->get_iocsr_as =3D get_iocsr_as; - licc->cpu_by_arch_id =3D cpu_by_arch_id; + licc->cpu_by_arch_id =3D loongson_cpu_by_arch_id; } =20 static const TypeInfo loongson_ipi_types[] =3D { diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c index a6ce0181f6..2f574947ef 100644 --- a/hw/intc/loongson_ipi_common.c +++ b/hw/intc/loongson_ipi_common.c @@ -105,16 +105,17 @@ static MemTxResult mail_send(LoongsonIPICommonState *= ipi, uint32_t cpuid; hwaddr addr; CPUState *cs; + int cpu, ret; =20 cpuid =3D extract32(val, 16, 10); - cs =3D licc->cpu_by_arch_id(cpuid); - if (cs =3D=3D NULL) { + ret =3D licc->cpu_by_arch_id(ipi, cpuid, &cpu, &cs); + if (ret !=3D MEMTX_OK) { return MEMTX_DECODE_ERROR; } =20 /* override requester_id */ addr =3D SMP_IPI_MAILBOX + CORE_BUF_20 + (val & 0x1c); - attrs.requester_id =3D cs->cpu_index; + attrs.requester_id =3D cpu; return send_ipi_data(ipi, cs, val, addr, attrs); } =20 @@ -125,16 +126,17 @@ static MemTxResult any_send(LoongsonIPICommonState *i= pi, uint32_t cpuid; hwaddr addr; CPUState *cs; + int cpu, ret; =20 cpuid =3D extract32(val, 16, 10); - cs =3D licc->cpu_by_arch_id(cpuid); - if (cs =3D=3D NULL) { + ret =3D licc->cpu_by_arch_id(ipi, cpuid, &cpu, &cs); + if (ret !=3D MEMTX_OK) { return MEMTX_DECODE_ERROR; } =20 /* override requester_id */ addr =3D val & 0xffff; - attrs.requester_id =3D cs->cpu_index; + attrs.requester_id =3D cpu; return send_ipi_data(ipi, cs, val, addr, attrs); } =20 @@ -148,6 +150,7 @@ MemTxResult loongson_ipi_core_writel(void *opaque, hwad= dr addr, uint64_t val, uint32_t cpuid; uint8_t vector; CPUState *cs; + int cpu, ret; =20 addr &=3D 0xff; trace_loongson_ipi_write(size, (uint64_t)addr, val); @@ -178,11 +181,11 @@ MemTxResult loongson_ipi_core_writel(void *opaque, hw= addr addr, uint64_t val, cpuid =3D extract32(val, 16, 10); /* IPI status vector */ vector =3D extract8(val, 0, 5); - cs =3D licc->cpu_by_arch_id(cpuid); - if (cs =3D=3D NULL || cs->cpu_index >=3D ipi->num_cpu) { + ret =3D licc->cpu_by_arch_id(ipi, cpuid, &cpu, &cs); + if (ret !=3D MEMTX_OK || cpu >=3D ipi->num_cpu) { return MEMTX_DECODE_ERROR; } - loongson_ipi_core_writel(&ipi->cpu[cs->cpu_index], CORE_SET_OFF, + loongson_ipi_core_writel(&ipi->cpu[cpu], CORE_SET_OFF, BIT(vector), 4, attrs); break; default: diff --git a/include/hw/intc/loongson_ipi_common.h b/include/hw/intc/loongs= on_ipi_common.h index df9d9c5168..2f1646a5f9 100644 --- a/include/hw/intc/loongson_ipi_common.h +++ b/include/hw/intc/loongson_ipi_common.h @@ -44,7 +44,8 @@ struct LoongsonIPICommonClass { DeviceRealize parent_realize; DeviceUnrealize parent_unrealize; AddressSpace *(*get_iocsr_as)(CPUState *cpu); - CPUState *(*cpu_by_arch_id)(int64_t id); + int (*cpu_by_arch_id)(LoongsonIPICommonState *lics, int64_t id, + int *index, CPUState **pcs); }; =20 MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *d= ata, --=20 2.39.3