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Tue, 26 Nov 2024 21:35:41 -0800 (PST) From: baturo.alexey@gmail.com To: Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org, zhiwei_liu@linux.alibaba.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, alistair23@gmail.com, frank.chang@sifive.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v11 6/7] target/riscv: Apply pointer masking for virtualized memory accesses Date: Wed, 27 Nov 2024 08:35:22 +0300 Message-Id: <20241127053523.397378-7-baturo.alexey@gmail.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241127053523.397378-1-baturo.alexey@gmail.com> References: <20241127053523.397378-1-baturo.alexey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::132; envelope-from=baturo.alexey@gmail.com; helo=mail-lf1-x132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1732685794749019100 Content-Type: text/plain; charset="utf-8" From: Alexey Baturo Signed-off-by: Alexey Baturo --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_helper.c | 19 +++++++++++++++++++ target/riscv/insn_trans/trans_rvh.c.inc | 11 +++++++++++ target/riscv/translate.c | 4 ++++ 4 files changed, 36 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 11e3a6d647..6bbd9c6c25 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -634,6 +634,7 @@ FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1) /* If pointer masking should be applied and address sign extended */ FIELD(TB_FLAGS, PM_PMM, 29, 2) FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1) +FIELD(TB_FLAGS, PM_VPMM, 32, 2) =20 #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) @@ -773,6 +774,7 @@ bool riscv_cpu_is_32bit(RISCVCPU *cpu); =20 bool riscv_cpu_virt_mem_enabled(CPURISCVState *env); RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env); +RISCVPmPmm riscv_pm_get_virt_pmm(CPURISCVState *env); int riscv_pm_get_pmlen(RISCVPmPmm pmm); =20 RISCVException riscv_csrr(CPURISCVState *env, int csrno, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 78b461a5cf..4065809d9f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -213,6 +213,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, flags =3D FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); flags =3D FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); + flags =3D FIELD_DP64(flags, TB_FLAGS, PM_VPMM, riscv_pm_get_virt_pmm(e= nv)); =20 *pflags =3D flags; } @@ -260,6 +261,24 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) return pmm; } =20 +RISCVPmPmm riscv_pm_get_virt_pmm(CPURISCVState *env) +{ + RISCVPmPmm pmm =3D PMM_FIELD_DISABLED; +#ifndef CONFIG_USER_ONLY + int priv_mode =3D cpu_address_mode(env); + if (priv_mode =3D=3D PRV_U) { + pmm =3D get_field(env->hstatus, HSTATUS_HUPMM); + } else { + if (get_field(env->hstatus, HSTATUS_SPVP)) { + pmm =3D get_field(env->henvcfg, HENVCFG_PMM); + } else { + pmm =3D get_field(env->senvcfg, SENVCFG_PMM); + } + } +#endif + return pmm; +} + bool riscv_cpu_virt_mem_enabled(CPURISCVState *env) { bool virt_mem_en =3D false; diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_tr= ans/trans_rvh.c.inc index 03c6694430..ae067789d1 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -44,6 +44,14 @@ static bool do_hlv(DisasContext *ctx, arg_r2 *a, TCGv dest =3D dest_gpr(ctx, a->rd); TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); =20 + bool is_hlvx =3D (func =3D=3D gen_helper_hyp_hlvx_hu) || + (func =3D=3D gen_helper_hyp_hlvx_wu); + + /* Apply Zjpm pointer masking */ + if (!is_hlvx) { + tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_vxl); + } + decode_save_opc(ctx, 0); func(dest, tcg_env, addr); gen_set_gpr(ctx, a->rd, dest); @@ -56,6 +64,9 @@ static bool do_hsv(DisasContext *ctx, arg_r2_s *a, TCGv addr =3D get_gpr(ctx, a->rs1, EXT_NONE); TCGv data =3D get_gpr(ctx, a->rs2, EXT_NONE); =20 + /* Apply Zjpm pointer masking */ + tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_vxl); + decode_save_opc(ctx, 0); func(tcg_env, addr, data); return true; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 32df295123..d8f83315c6 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -104,6 +104,7 @@ typedef struct DisasContext { TCGv zero; /* actual address width */ uint8_t addr_xl; + uint8_t addr_vxl; bool addr_signed; /* Ztso */ bool ztso; @@ -1239,10 +1240,13 @@ static void riscv_tr_init_disas_context(DisasContex= tBase *dcbase, CPUState *cs) ctx->cs =3D cs; if (get_xl(ctx) =3D=3D MXL_RV32) { ctx->addr_xl =3D 32; + ctx->addr_vxl =3D 32; ctx->addr_signed =3D false; } else { int pm_pmm =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_PMM); ctx->addr_xl =3D 64 - riscv_pm_get_pmlen(pm_pmm); + int pm_vpmm =3D FIELD_EX64(tb_flags, TB_FLAGS, PM_VPMM); + ctx->addr_vxl =3D 64 - riscv_pm_get_pmlen(pm_vpmm); ctx->addr_signed =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_SIGNEXTEND); } ctx->ztso =3D cpu->cfg.ext_ztso; --=20 2.39.5