From nobody Sat Nov 23 18:40:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1732245806; cv=none; d=zohomail.com; s=zohoarc; b=Rw0+C1SVAUxstGO+izsUa70j4R7ECkRRAyDxP2qfqH5gQze56lc1xuxGAvzVcIpnthpnsu67th3S3Vq2G774WvqeRp2ZLHsJOuZs0B2YxCcXLyHta61hzbsGj5NuZhz885T5ia+M1u2klRaWD71YfeBG8Dghi7s7OZtuDUoXED8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1732245806; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=F5dz25xLBEpscPUFsdwI6ZdGbDCjYWaBqQIsk/OC0sI=; b=U4+97Uvcia47qU5X0d6EvrvrQNm+J3kNS4dJTgllRuF/i7TAosYX4ig5sU7sxLVCmxFRbQG33GNHRHVi6zjst7cJBuTuhddFHZmTWjWBB3nV6z4tmn/7diULRCYqGFkL4U7m6FuJIOsb8Ncb2NmWomVIfJkWlJcFrsYts0xcZ/M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1732245806140113.6575822551946; Thu, 21 Nov 2024 19:23:26 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tEKFi-0005WN-FX; Thu, 21 Nov 2024 22:22:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tEKFf-0005Vy-To for qemu-devel@nongnu.org; Thu, 21 Nov 2024 22:22:35 -0500 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tEKFd-0003wm-Sv for qemu-devel@nongnu.org; Thu, 21 Nov 2024 22:22:35 -0500 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-720c286bcd6so1496133b3a.3 for ; Thu, 21 Nov 2024 19:22:32 -0800 (PST) Received: from fchang-1826.internal.sifive.com ([136.226.240.187]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2129dc157f3sm5506905ad.203.2024.11.21.19.22.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Nov 2024 19:22:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1732245751; x=1732850551; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F5dz25xLBEpscPUFsdwI6ZdGbDCjYWaBqQIsk/OC0sI=; b=YCPOTccKG4fCh5DtoSzE3vHMtnSw4cNd1mBioygJBq6QCMlbvQsvCDHo60JAZJABmx kdJwC8UjuAuh2MyU7UKmKy7xUBaNcQetsgGYifmPHrEwXDpQQaObNh/IZtllr7uWh99n MDQW/2/yMOcoB5ZDJesdmb4tIPQNs+9S0D04blu6s0rogSZtu0rtD+RYpKKxqt0oFG9r YeLC3D8rB75SJj1Bb5MirzHdIyKk+EWH3QPfiwgu2Lpez4XXWgrDNGoM0SnRKHDGxEAg YjENB1z+r6y7rWS7cdLzGMrfsMxr63bt4BMPGFhBqRMfLvjXqAsx357FALRzjnm383QJ h/4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732245751; x=1732850551; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F5dz25xLBEpscPUFsdwI6ZdGbDCjYWaBqQIsk/OC0sI=; b=X5MEMPAx8FXRzyqpVN/SlP5NdomTWB38S3KXGaEPpYE1qeKHZdgJJxeMjhFiPCN8rY E4kS9KC5el9+WXDXleFx2AjaD8Ls3gUVKnW9pQUR3rka0cr0Hm0XBcVW3K5U++abfQ4y n5MiYbn6Dm5tPoj2HomAFRwvvQu7miYgLj+yRxwNJsxVps7a6IMOCkxXfwTVKCZEo7yi EOjtbaTf+WSlITyTw5KjKF8fZUILX5IB4ej9EsS+eW1UofuYjmlV5NVygFxWxIcYmCSf bVC7gNJgAeahjlfySPlYEFBRVJuokLNO7aOWavPGUBLj3n8zupXUnDVWkNAlvsIOJy1Q Ukhw== X-Gm-Message-State: AOJu0Yzaoq78KHaUCMVykYf7qbJyRc7Pk+6hKpJhg0LlAXTJnDctNjbw dim6FOxfWPUWDCHOVYXdB7YWp8kmQJzb+BQnKJ7twtgTxeTm7AizfsCziEDCwrEbILcrki3Pyct fGCQZN7d9RPcCu2p7mDlk0Oa081pJqU4VvoavNM3i72bUrU36gQizJKNj6iWdNxkw6pfwoDaHdJ iY0/6puhaqMHJF79sK6iRhGluBrL3iJve8q3oUDLDlbIfn X-Gm-Gg: ASbGncu2EEhWhSqbkLMPrTHw2eetzaN/W/GglLNQ+JhWPlcryPyolMrT91DtoaHzkLN /eGJ+EIg/hGfNAJSEh/bToJSzdekdl/EFj+SNQzOqL2kMuiWGOj7BAOrcfGpd4s8X+yjXcXIbms 4l4QSPOxw6re6+nvSXz+QT6qS99b5ACaLcwDa6J8kYB+sV1ykzM+VSke1IeufC6hIIgtFHM+e0F /iX9vaiCwJp3hbn/QGHVk1GXqQhIpLaiUBDInqqmLUpKYBl2KRny6hsl/8W6TQWNTwu27bK7XwB GhTL5w== X-Google-Smtp-Source: AGHT+IFdtxnVWwp1P7K81MudpUg34Yz++DiRVsHh96tjlIQYkHhO9QY3DDf08Er6V00Coz7P8yHRWA== X-Received: by 2002:a17:902:e54f:b0:212:3f36:d985 with SMTP id d9443c01a7336-2129f82ea85mr17392975ad.53.1732245751038; Thu, 21 Nov 2024 19:22:31 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Tommy Wu , Frank Chang , Alistair Francis Subject: [PATCH v9 2/6] target/riscv: Add Smrnmi CSRs Date: Fri, 22 Nov 2024 11:22:13 +0800 Message-Id: <20241122032217.3816540-3-frank.chang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241122032217.3816540-1-frank.chang@sifive.com> References: <20241122032217.3816540-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1732245808416116600 Content-Type: text/plain; charset="utf-8" From: Tommy Wu The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause', 'mnstatus' CSRs. Signed-off-by: Frank Chang Signed-off-by: Tommy Wu Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 5 +++ target/riscv/cpu.h | 7 ++++ target/riscv/cpu_bits.h | 11 ++++++ target/riscv/csr.c | 82 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 105 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f219f0c3b5..c404828ca0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1029,6 +1029,11 @@ static void riscv_cpu_reset_hold(Object *obj, ResetT= ype type) riscv_trigger_reset_hold(env); } =20 + if (cpu->cfg.ext_smrnmi) { + env->rnmip =3D 0; + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_NMIE, false); + } + if (kvm_enabled()) { kvm_riscv_reset_vcpu(cpu); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 284b112821..a2cb471b3c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -486,6 +486,13 @@ struct CPUArchState { uint64_t kvm_timer_state; uint64_t kvm_timer_frequency; #endif /* CONFIG_KVM */ + + /* RNMI */ + target_ulong mnscratch; + target_ulong mnepc; + target_ulong mncause; /* mncause without bit XLEN-1 set to 1 */ + target_ulong mnstatus; + target_ulong rnmip; }; =20 /* diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 385a2c67c2..e69cf4f394 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -353,6 +353,12 @@ #define CSR_PMPADDR14 0x3be #define CSR_PMPADDR15 0x3bf =20 +/* RNMI */ +#define CSR_MNSCRATCH 0x740 +#define CSR_MNEPC 0x741 +#define CSR_MNCAUSE 0x742 +#define CSR_MNSTATUS 0x744 + /* Debug/Trace Registers (shared with Debug Mode) */ #define CSR_TSELECT 0x7a0 #define CSR_TDATA1 0x7a1 @@ -633,6 +639,11 @@ typedef enum { #define SATP64_ASID 0x0FFFF00000000000ULL #define SATP64_PPN 0x00000FFFFFFFFFFFULL =20 +/* RNMI mnstatus CSR mask */ +#define MNSTATUS_NMIE 0x00000008 +#define MNSTATUS_MNPV 0x00000080 +#define MNSTATUS_MNPP 0x00001800 + /* VM modes (satp.mode) privileged ISA 1.10 */ #define VM_1_10_MBARE 0 #define VM_1_10_SV32 1 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9846770820..5d8d0d7514 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -597,6 +597,17 @@ static RISCVException debug(CPURISCVState *env, int cs= rno) =20 return RISCV_EXCP_ILLEGAL_INST; } + +static RISCVException rnmi(CPURISCVState *env, int csrno) +{ + RISCVCPU *cpu =3D env_archcpu(env); + + if (cpu->cfg.ext_smrnmi) { + return RISCV_EXCP_NONE; + } + + return RISCV_EXCP_ILLEGAL_INST; +} #endif =20 static RISCVException seed(CPURISCVState *env, int csrno) @@ -4647,6 +4658,67 @@ static RISCVException write_upmbase(CPURISCVState *e= nv, int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException read_mnscratch(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->mnscratch; + return RISCV_EXCP_NONE; +} + +static int write_mnscratch(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mnscratch =3D val; + return RISCV_EXCP_NONE; +} + +static int read_mnepc(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mnepc; + return RISCV_EXCP_NONE; +} + +static int write_mnepc(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mnepc =3D val; + return RISCV_EXCP_NONE; +} + +static int read_mncause(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mncause; + return RISCV_EXCP_NONE; +} + +static int write_mncause(CPURISCVState *env, int csrno, target_ulong val) +{ + env->mncause =3D val; + return RISCV_EXCP_NONE; +} + +static int read_mnstatus(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->mnstatus; + return RISCV_EXCP_NONE; +} + +static int write_mnstatus(CPURISCVState *env, int csrno, target_ulong val) +{ + target_ulong mask =3D (MNSTATUS_NMIE | MNSTATUS_MNPP); + + if (riscv_has_ext(env, RVH)) { + /* Flush tlb on mnstatus fields that affect VM. */ + if ((val ^ env->mnstatus) & MNSTATUS_MNPV) { + tlb_flush(env_cpu(env)); + } + + mask |=3D MNSTATUS_MNPV; + } + + /* mnstatus.mnie can only be cleared by hardware. */ + env->mnstatus =3D (env->mnstatus & MNSTATUS_NMIE) | (val & mask); + return RISCV_EXCP_NONE; +} + #endif =20 /* Crypto Extension */ @@ -5154,6 +5226,16 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { write_sstateen_1_3, .min_priv_ver =3D PRIV_VERSION_1_12_0 }, =20 + /* RNMI */ + [CSR_MNSCRATCH] =3D { "mnscratch", rnmi, read_mnscratch, write_mnscrat= ch, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_MNEPC] =3D { "mnepc", rnmi, read_mnepc, write_mnepc, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_MNCAUSE] =3D { "mncause", rnmi, read_mncause, write_mncause, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + [CSR_MNSTATUS] =3D { "mnstatus", rnmi, read_mnstatus, write_mnstatu= s, + .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, + /* Supervisor Trap Setup */ [CSR_SSTATUS] =3D { "sstatus", smode, read_sstatus, write_sst= atus, NULL, read_sstatus_i128 = }, --=20 2.34.1