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Thu, 21 Nov 2024 17:31:00 -0800 (PST) Subject: [PATCH] target/riscv: Don't start user-mode with VILL Date: Thu, 21 Nov 2024 16:32:47 -0800 Message-ID: <20241122003247.8955-1-palmer@rivosinc.com> X-Mailer: git-send-email 2.45.2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Cc: Palmer Dabbelt From: Palmer Dabbelt To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=palmer@rivosinc.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1732239131263116600 Content-Type: text/plain; charset="utf-8" This is still under discussion in the psABI, but it's looking like we're going to forbid VILL in userspace in order to maintain compatibility with binaries that don't expect implementations to trap whole register moves under VILL (as in QEMU before 4eff52cd46 ("target/riscv: Add vill check for whole vector register move instructions"), for example). Fixes: f8c1f36a2e ("target/riscv: Set vtype.vill on CPU reset") Link: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/454 Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f219f0c3b5..d19a44de99 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1022,7 +1022,11 @@ static void riscv_cpu_reset_hold(Object *obj, ResetT= ype type) cs->exception_index =3D RISCV_EXCP_NONE; env->load_res =3D -1; set_default_nan_mode(1, &env->fp_status); +#ifdef CONFIG_USER_ONLY + env->vill =3D false; +#else env->vill =3D true; +#endif =20 #ifndef CONFIG_USER_ONLY if (cpu->cfg.debug) { --=20 2.45.2