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Date: Wed, 20 Nov 2024 23:39:33 +0800 Message-Id: <20241120153935.24706-2-jim.shu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241120153935.24706-1-jim.shu@sifive.com> References: <20241120153935.24706-1-jim.shu@sifive.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=jim.shu@sifive.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1732117236035116600 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Larger initrd image will overlap the DTB at 3GB address. Since 64-bit system doesn't have 32-bit addressable issue, we just load DTB to the end of dram in 64-bit system. Signed-off-by: Jim Shu --- hw/riscv/boot.c | 14 +++++++++----- hw/riscv/microchip_pfsoc.c | 4 ++-- hw/riscv/sifive_u.c | 4 ++-- hw/riscv/spike.c | 4 ++-- hw/riscv/virt.c | 2 +- include/hw/riscv/boot.h | 2 +- 6 files changed, 17 insertions(+), 13 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 2e319168db..d36d3a7104 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -293,7 +293,7 @@ out: * The FDT is fdt_packed() during the calculation. */ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, - MachineState *ms) + MachineState *ms, RISCVHartArrayState *har= ts) { int ret =3D fdt_pack(ms->fdt); hwaddr dram_end, temp; @@ -317,11 +317,15 @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwa= ddr dram_size, =20 /* * We should put fdt as far as possible to avoid kernel/initrd overwri= ting - * its content. But it should be addressable by 32 bit system as well. - * Thus, put it at an 2MB aligned address that less than fdt size from= the - * end of dram or 3GB whichever is lesser. + * its content. But it should be addressable by 32 bit system as well = in RV32. + * Thus, put it near to the end of dram in RV64, and put it near to th= e end + * of dram or 3GB whichever is lesser in RV32. */ - temp =3D (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_e= nd; + if (!riscv_is_32bit(harts)) { + temp =3D dram_end; + } else { + temp =3D (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dr= am_end; + } =20 return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); } diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index f9a3b43d2e..ba8b0a2c26 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -519,7 +519,7 @@ static void microchip_icicle_kit_machine_init(MachineSt= ate *machine) bool kernel_as_payload =3D false; target_ulong firmware_end_addr, kernel_start_addr; uint64_t kernel_entry; - uint32_t fdt_load_addr; + uint64_t fdt_load_addr; DriveInfo *dinfo =3D drive_get(IF_SD, 0, 0); =20 /* Sanity check on RAM size */ @@ -625,7 +625,7 @@ static void microchip_icicle_kit_machine_init(MachineSt= ate *machine) /* Compute the fdt load address in dram */ fdt_load_addr =3D riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DR= AM_LO].base, memmap[MICROCHIP_PFSOC_DRAM= _LO].size, - machine); + machine, &s->soc.u_cpus); riscv_load_fdt(fdt_load_addr, machine->fdt); =20 /* Load the reset vector */ diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index c5e74126b1..05467e833a 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -519,7 +519,7 @@ static void sifive_u_machine_init(MachineState *machine) const char *firmware_name; uint32_t start_addr_hi32 =3D 0x00000000; int i; - uint32_t fdt_load_addr; + uint64_t fdt_load_addr; uint64_t kernel_entry; DriveInfo *dinfo; BlockBackend *blk; @@ -606,7 +606,7 @@ static void sifive_u_machine_init(MachineState *machine) =20 fdt_load_addr =3D riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].bas= e, memmap[SIFIVE_U_DEV_DRAM].size, - machine); + machine, &s->soc.u_cpus); riscv_load_fdt(fdt_load_addr, machine->fdt); =20 if (!riscv_is_32bit(&s->soc.u_cpus)) { diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index fceb91d946..acd7ab1ae1 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -201,7 +201,7 @@ static void spike_board_init(MachineState *machine) hwaddr firmware_load_addr =3D memmap[SPIKE_DRAM].base; target_ulong kernel_start_addr; char *firmware_name; - uint32_t fdt_load_addr; + uint64_t fdt_load_addr; uint64_t kernel_entry; char *soc_name; int i, base_hartid, hart_count; @@ -317,7 +317,7 @@ static void spike_board_init(MachineState *machine) =20 fdt_load_addr =3D riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base, memmap[SPIKE_DRAM].size, - machine); + machine, &s->soc[0]); riscv_load_fdt(fdt_load_addr, machine->fdt); =20 /* load the reset vector */ diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 45a8c4f819..761bce3304 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1424,7 +1424,7 @@ static void virt_machine_done(Notifier *notifier, voi= d *data) =20 fdt_load_addr =3D riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, memmap[VIRT_DRAM].size, - machine); + machine, &s->soc[0]); riscv_load_fdt(fdt_load_addr, machine->fdt); =20 /* load the reset vector */ diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index f778b560de..34a80c5ff4 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -49,7 +49,7 @@ target_ulong riscv_load_kernel(MachineState *machine, bool load_initrd, symbol_fn_t sym_cb); uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, - MachineState *ms); + MachineState *ms, RISCVHartArrayState *har= ts); void riscv_load_fdt(hwaddr fdt_addr, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState = *harts, hwaddr saddr, --=20 2.17.1 From nobody Sat Nov 23 15:50:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Signed-off-by: Jim Shu --- hw/riscv/boot.c | 65 ++++++++++++++++++++++---------------- hw/riscv/microchip_pfsoc.c | 11 ++++--- hw/riscv/opentitan.c | 4 ++- hw/riscv/sifive_e.c | 4 ++- hw/riscv/sifive_u.c | 12 ++++--- hw/riscv/spike.c | 12 ++++--- hw/riscv/virt.c | 13 +++++--- include/hw/riscv/boot.h | 25 ++++++++++----- 8 files changed, 90 insertions(+), 56 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index d36d3a7104..81d27f935e 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -67,9 +67,15 @@ char *riscv_plic_hart_config_string(int hart_count) return g_strjoinv(",", (char **)vals); } =20 -target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, +void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts) +{ + info->kernel_size =3D 0; + info->is_32bit =3D riscv_is_32bit(harts); +} + +target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info, target_ulong firmware_end_addr) { - if (riscv_is_32bit(harts)) { + if (info->is_32bit) { return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); } else { return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB); @@ -175,7 +181,7 @@ target_ulong riscv_load_firmware(const char *firmware_f= ilename, exit(1); } =20 -static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) +static void riscv_load_initrd(MachineState *machine, RISCVBootInfo *info) { const char *filename =3D machine->initrd_filename; uint64_t mem_size =3D machine->ram_size; @@ -196,7 +202,7 @@ static void riscv_load_initrd(MachineState *machine, ui= nt64_t kernel_entry) * halfway into RAM, and for boards with 1GB of RAM or more we put * the initrd at 512MB. */ - start =3D kernel_entry + MIN(mem_size / 2, 512 * MiB); + start =3D info->image_low_addr + MIN(mem_size / 2, 512 * MiB); =20 size =3D load_ramdisk(filename, start, mem_size - start); if (size =3D=3D -1) { @@ -215,14 +221,14 @@ static void riscv_load_initrd(MachineState *machine, = uint64_t kernel_entry) } } =20 -target_ulong riscv_load_kernel(MachineState *machine, - RISCVHartArrayState *harts, - target_ulong kernel_start_addr, - bool load_initrd, - symbol_fn_t sym_cb) +void riscv_load_kernel(MachineState *machine, + RISCVBootInfo *info, + target_ulong kernel_start_addr, + bool load_initrd, + symbol_fn_t sym_cb) { const char *kernel_filename =3D machine->kernel_filename; - uint64_t kernel_load_base, kernel_entry; + ssize_t kernel_size; void *fdt =3D machine->fdt; =20 g_assert(kernel_filename !=3D NULL); @@ -234,21 +240,28 @@ target_ulong riscv_load_kernel(MachineState *machine, * the (expected) load address load address. This allows kernels to ha= ve * separate SBI and ELF entry points (used by FreeBSD, for example). */ - if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, - NULL, &kernel_load_base, NULL, NULL, 0, - EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { - kernel_entry =3D kernel_load_base; + kernel_size =3D load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NU= LL, + &info->image_low_addr, &info->image_hig= h_addr, + NULL, 0, EM_RISCV, 1, 0, NULL, true, sy= m_cb); + if (kernel_size > 0) { + info->kernel_size =3D kernel_size; goto out; } =20 - if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, - NULL, NULL, NULL) > 0) { + kernel_size =3D load_uimage_as(kernel_filename, &info->image_low_addr, + NULL, NULL, NULL, NULL, NULL); + if (kernel_size > 0) { + info->kernel_size =3D kernel_size; + info->image_high_addr =3D info->image_low_addr + kernel_size; goto out; } =20 - if (load_image_targphys_as(kernel_filename, kernel_start_addr, - current_machine->ram_size, NULL) > 0) { - kernel_entry =3D kernel_start_addr; + kernel_size =3D load_image_targphys_as(kernel_filename, kernel_start_a= ddr, + current_machine->ram_size, NULL); + if (kernel_size > 0) { + info->kernel_size =3D kernel_size; + info->image_low_addr =3D kernel_start_addr; + info->image_high_addr =3D info->image_low_addr + kernel_size; goto out; } =20 @@ -257,23 +270,21 @@ target_ulong riscv_load_kernel(MachineState *machine, =20 out: /* - * For 32 bit CPUs 'kernel_entry' can be sign-extended by + * For 32 bit CPUs 'image_low_addr' can be sign-extended by * load_elf_ram_sym(). */ - if (riscv_is_32bit(harts)) { - kernel_entry =3D extract64(kernel_entry, 0, 32); + if (info->is_32bit) { + info->image_low_addr =3D extract64(info->image_low_addr, 0, 32); } =20 if (load_initrd && machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); + riscv_load_initrd(machine, info); } =20 if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) { qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", machine->kernel_cmdline); } - - return kernel_entry; } =20 /* @@ -293,7 +304,7 @@ out: * The FDT is fdt_packed() during the calculation. */ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, - MachineState *ms, RISCVHartArrayState *har= ts) + MachineState *ms, RISCVBootInfo *info) { int ret =3D fdt_pack(ms->fdt); hwaddr dram_end, temp; @@ -321,7 +332,7 @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwadd= r dram_size, * Thus, put it near to the end of dram in RV64, and put it near to th= e end * of dram or 3GB whichever is lesser in RV32. */ - if (!riscv_is_32bit(harts)) { + if (!info->is_32bit) { temp =3D dram_end; } else { temp =3D (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dr= am_end; diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index ba8b0a2c26..a302965b6d 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -521,6 +521,7 @@ static void microchip_icicle_kit_machine_init(MachineSt= ate *machine) uint64_t kernel_entry; uint64_t fdt_load_addr; DriveInfo *dinfo =3D drive_get(IF_SD, 0, 0); + RISCVBootInfo boot_info; =20 /* Sanity check on RAM size */ if (machine->ram_size < mc->default_ram_size) { @@ -615,17 +616,19 @@ static void microchip_icicle_kit_machine_init(Machine= State *machine) firmware_end_addr =3D riscv_find_and_load_firmware(machine, firmware_n= ame, &firmware_load_addr, = NULL); =20 + riscv_boot_info_init(&boot_info, &s->soc.u_cpus); if (kernel_as_payload) { - kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpus, + kernel_start_addr =3D riscv_calc_kernel_start_addr(&boot_info, firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine, &s->soc.u_cpus, - kernel_start_addr, true, NULL); + riscv_load_kernel(machine, &boot_info, kernel_start_addr, + true, NULL); + kernel_entry =3D boot_info.image_low_addr; =20 /* Compute the fdt load address in dram */ fdt_load_addr =3D riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DR= AM_LO].base, memmap[MICROCHIP_PFSOC_DRAM= _LO].size, - machine, &s->soc.u_cpus); + machine, &boot_info); riscv_load_fdt(fdt_load_addr, machine->fdt); =20 /* Load the reset vector */ diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index e2830e9dc2..57f899464b 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -81,6 +81,7 @@ static void opentitan_machine_init(MachineState *machine) OpenTitanState *s =3D OPENTITAN_MACHINE(machine); const MemMapEntry *memmap =3D ibex_memmap; MemoryRegion *sys_mem =3D get_system_memory(); + RISCVBootInfo boot_info; =20 if (machine->ram_size !=3D mc->default_ram_size) { char *sz =3D size_to_str(mc->default_ram_size); @@ -102,8 +103,9 @@ static void opentitan_machine_init(MachineState *machin= e) riscv_load_firmware(machine->firmware, &firmware_load_addr, NULL); } =20 + riscv_boot_info_init(&boot_info, &s->soc.cpus); if (machine->kernel_filename) { - riscv_load_kernel(machine, &s->soc.cpus, + riscv_load_kernel(machine, &boot_info, memmap[IBEX_DEV_RAM].base, false, NULL); } diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 5a1959f2a9..ebcd33ab95 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -78,6 +78,7 @@ static void sifive_e_machine_init(MachineState *machine) SiFiveEState *s =3D RISCV_E_MACHINE(machine); MemoryRegion *sys_mem =3D get_system_memory(); int i; + RISCVBootInfo boot_info; =20 if (machine->ram_size !=3D mc->default_ram_size) { char *sz =3D size_to_str(mc->default_ram_size); @@ -113,8 +114,9 @@ static void sifive_e_machine_init(MachineState *machine) rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), memmap[SIFIVE_E_DEV_MROM].base, &address_space_m= emory); =20 + riscv_boot_info_init(&boot_info, &s->soc.cpus); if (machine->kernel_filename) { - riscv_load_kernel(machine, &s->soc.cpus, + riscv_load_kernel(machine, &boot_info, memmap[SIFIVE_E_DEV_DTIM].base, false, NULL); } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 05467e833a..0a77faaf6e 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -525,6 +525,7 @@ static void sifive_u_machine_init(MachineState *machine) BlockBackend *blk; DeviceState *flash_dev, *sd_dev, *card_dev; qemu_irq flash_cs, sd_cs; + RISCVBootInfo boot_info; =20 /* Initialize SoC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_= SOC); @@ -590,12 +591,13 @@ static void sifive_u_machine_init(MachineState *machi= ne) firmware_end_addr =3D riscv_find_and_load_firmware(machine, firmware_n= ame, &start_addr, NULL); =20 + riscv_boot_info_init(&boot_info, &s->soc.u_cpus); if (machine->kernel_filename) { - kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpus, + kernel_start_addr =3D riscv_calc_kernel_start_addr(&boot_info, firmware_end_addr= ); - - kernel_entry =3D riscv_load_kernel(machine, &s->soc.u_cpus, - kernel_start_addr, true, NULL); + riscv_load_kernel(machine, &boot_info, kernel_start_addr, + true, NULL); + kernel_entry =3D boot_info.image_low_addr; } else { /* * If dynamic firmware is used, it doesn't know where is the next m= ode @@ -606,7 +608,7 @@ static void sifive_u_machine_init(MachineState *machine) =20 fdt_load_addr =3D riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].bas= e, memmap[SIFIVE_U_DEV_DRAM].size, - machine, &s->soc.u_cpus); + machine, &boot_info); riscv_load_fdt(fdt_load_addr, machine->fdt); =20 if (!riscv_is_32bit(&s->soc.u_cpus)) { diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index acd7ab1ae1..c3ad16d316 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -206,6 +206,7 @@ static void spike_board_init(MachineState *machine) char *soc_name; int i, base_hartid, hart_count; bool htif_custom_base =3D false; + RISCVBootInfo boot_info; =20 /* Check socket count limit */ if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) { @@ -300,13 +301,14 @@ static void spike_board_init(MachineState *machine) create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base); =20 /* Load kernel */ + riscv_boot_info_init(&boot_info, &s->soc[0]); if (machine->kernel_filename) { - kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], + kernel_start_addr =3D riscv_calc_kernel_start_addr(&boot_info, firmware_end_addr= ); =20 - kernel_entry =3D riscv_load_kernel(machine, &s->soc[0], - kernel_start_addr, - true, htif_symbol_callback); + riscv_load_kernel(machine, &boot_info, kernel_start_addr, + true, htif_symbol_callback); + kernel_entry =3D boot_info.image_low_addr; } else { /* * If dynamic firmware is used, it doesn't know where is the next m= ode @@ -317,7 +319,7 @@ static void spike_board_init(MachineState *machine) =20 fdt_load_addr =3D riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base, memmap[SPIKE_DRAM].size, - machine, &s->soc[0]); + machine, &boot_info); riscv_load_fdt(fdt_load_addr, machine->fdt); =20 /* load the reset vector */ diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 761bce3304..9190d1c3aa 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1366,6 +1366,7 @@ static void virt_machine_done(Notifier *notifier, voi= d *data) uint64_t fdt_load_addr; uint64_t kernel_entry =3D 0; BlockBackend *pflash_blk0; + RISCVBootInfo boot_info; =20 /* * An user provided dtb must include everything, including @@ -1414,17 +1415,19 @@ static void virt_machine_done(Notifier *notifier, v= oid *data) } } =20 + riscv_boot_info_init(&boot_info, &s->soc[0]); + if (machine->kernel_filename && !kernel_entry) { - kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], + kernel_start_addr =3D riscv_calc_kernel_start_addr(&boot_info, firmware_end_addr= ); - - kernel_entry =3D riscv_load_kernel(machine, &s->soc[0], - kernel_start_addr, true, NULL); + riscv_load_kernel(machine, &boot_info, kernel_start_addr, + true, NULL); + kernel_entry =3D boot_info.image_low_addr; } =20 fdt_load_addr =3D riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, memmap[VIRT_DRAM].size, - machine, &s->soc[0]); + machine, &boot_info); riscv_load_fdt(fdt_load_addr, machine->fdt); =20 /* load the reset vector */ diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 34a80c5ff4..06b51ed086 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -27,11 +27,20 @@ #define RISCV32_BIOS_BIN "opensbi-riscv32-generic-fw_dynamic.bin" #define RISCV64_BIOS_BIN "opensbi-riscv64-generic-fw_dynamic.bin" =20 +typedef struct RISCVBootInfo { + ssize_t kernel_size; + hwaddr image_low_addr; + hwaddr image_high_addr; + + bool is_32bit; +} RISCVBootInfo; + bool riscv_is_32bit(RISCVHartArrayState *harts); =20 char *riscv_plic_hart_config_string(int hart_count); =20 -target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, +void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts); +target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info, target_ulong firmware_end_addr); target_ulong riscv_find_and_load_firmware(MachineState *machine, const char *default_machine_firm= ware, @@ -43,13 +52,13 @@ char *riscv_find_firmware(const char *firmware_filename, target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr *firmware_load_addr, symbol_fn_t sym_cb); -target_ulong riscv_load_kernel(MachineState *machine, - RISCVHartArrayState *harts, - target_ulong firmware_end_addr, - bool load_initrd, - symbol_fn_t sym_cb); -uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, - MachineState *ms, RISCVHartArrayState *har= ts); +void riscv_load_kernel(MachineState *machine, + RISCVBootInfo *info, + target_ulong kernel_start_addr, + bool load_initrd, + symbol_fn_t sym_cb); +uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, + MachineState *ms, RISCVBootInfo *info); void riscv_load_fdt(hwaddr fdt_addr, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState = *harts, hwaddr saddr, --=20 2.17.1 From nobody Sat Nov 23 15:50:59 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1732117271; cv=none; d=zohomail.com; s=zohoarc; b=RHHvW3IeEfT4KqeCWf7FB8spsagExLrbrz2IKQ6Z754aW+urfo57fZy11DqovIToppSSJ35TQT+aV0cF5cYXOu4CCNXq4uqPwAaYVoaWRSg9osaJ3mnmwWePNstEi9Rfgep7w4xrK5cjSPV4zJrlH+TOtt2BN3MCjX21W0HLsgs= ARC-Message-Signature: i=1; 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Signed-off-by: Jim Shu --- hw/riscv/boot.c | 25 ++++++++++++++++++++++++- include/hw/riscv/boot.h | 3 +++ 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 81d27f935e..bc8074fec8 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -70,6 +70,7 @@ char *riscv_plic_hart_config_string(int hart_count) void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts) { info->kernel_size =3D 0; + info->initrd_size =3D 0; info->is_32bit =3D riscv_is_32bit(harts); } =20 @@ -213,6 +214,9 @@ static void riscv_load_initrd(MachineState *machine, RI= SCVBootInfo *info) } } =20 + info->initrd_start =3D start; + info->initrd_size =3D size; + /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ if (fdt) { end =3D start + size; @@ -309,6 +313,7 @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwadd= r dram_size, int ret =3D fdt_pack(ms->fdt); hwaddr dram_end, temp; int fdtsize; + uint64_t dtb_start, dtb_start_limit; =20 /* Should only fail if we've built a corrupted tree */ g_assert(ret =3D=3D 0); @@ -319,6 +324,17 @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwad= dr dram_size, exit(1); } =20 + if (info->initrd_size) { + /* If initrd is successfully loaded, place DTB after it. */ + dtb_start_limit =3D info->initrd_start + info->initrd_size; + } else if (info->kernel_size) { + /* If only kernel is successfully loaded, place DTB after it. */ + dtb_start_limit =3D info->image_high_addr; + } else { + /* Otherwise, do not check DTB overlapping */ + dtb_start_limit =3D 0; + } + /* * A dram_size =3D=3D 0, usually from a MemMapEntry[].size element, * means that the DRAM block goes all the way to ms->ram_size. @@ -338,7 +354,14 @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwad= dr dram_size, temp =3D (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dr= am_end; } =20 - return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); + dtb_start =3D QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); + + if (dtb_start_limit && (dtb_start < dtb_start_limit)) { + error_report("No enough memory to place DTB after kernel/initrd"); + exit(1); + } + + return dtb_start; } =20 /* diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 06b51ed086..7d59b2e6c6 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -32,6 +32,9 @@ typedef struct RISCVBootInfo { hwaddr image_low_addr; hwaddr image_high_addr; =20 + hwaddr initrd_start; + ssize_t initrd_size; + bool is_32bit; } RISCVBootInfo; =20 --=20 2.17.1