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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=89.207.88.253; envelope-from=ivan.klokov@syntacore.com; helo=mta-03.yadro.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, T_SPF_PERMERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @syntacore.com) (identity @syntacore.com) X-ZM-MESSAGEID: 1732087740438116600 Content-Type: text/plain; charset="utf-8" The RISC-V architecture supports the creation of custom CSR-mapped devices. It would be convenient to test them in the same way as MMIO-mapped devices. To do this, a new call has been added to read/write CSR registers. Signed-off-by: Ivan Klokov Acked-by: Fabiano Rosas Reviewed-by: Daniel Henrique Barboza --- hw/riscv/riscv_hart.c | 55 ++++++++++++++++++++++++++++++++++++++++++ tests/qtest/libqtest.c | 27 +++++++++++++++++++++ tests/qtest/libqtest.h | 14 +++++++++++ 3 files changed, 96 insertions(+) diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 613ea2aaa0..22cc8ae31f 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -21,6 +21,8 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" +#include "qemu/cutils.h" +#include "sysemu/qtest.h" #include "sysemu/reset.h" #include "hw/sysbus.h" #include "target/riscv/cpu.h" @@ -42,6 +44,55 @@ static void riscv_harts_cpu_reset(void *opaque) cpu_reset(CPU(cpu)); } =20 +#ifndef CONFIG_USER_ONLY +static void csr_call(char *cmd, uint64_t cpu_num, int csrno, uint64_t *val) +{ + RISCVCPU *cpu =3D RISCV_CPU(cpu_by_arch_id(cpu_num)); + CPURISCVState *env =3D &cpu->env; + + int ret =3D RISCV_EXCP_NONE; + if (strcmp(cmd, "get_csr") =3D=3D 0) { + ret =3D riscv_csrr(env, csrno, (target_ulong *)val); + } else if (strcmp(cmd, "set_csr") =3D=3D 0) { + ret =3D riscv_csrrw(env, csrno, NULL, *(target_ulong *)val, + MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); + } + + g_assert(ret =3D=3D RISCV_EXCP_NONE); +} + +static bool csr_qtest_callback(CharBackend *chr, gchar **words) +{ + if (strcmp(words[0], "csr") =3D=3D 0) { + + uint64_t cpu; + uint64_t val; + int rc, csr; + + rc =3D qemu_strtou64(words[2], NULL, 0, &cpu); + g_assert(rc =3D=3D 0); + rc =3D qemu_strtoi(words[3], NULL, 0, &csr); + g_assert(rc =3D=3D 0); + rc =3D qemu_strtou64(words[4], NULL, 0, &val); + g_assert(rc =3D=3D 0); + csr_call(words[1], cpu, csr, &val); + + qtest_send_prefix(chr); + qtest_sendf(chr, "OK 0 "TARGET_FMT_lx"\n", (target_ulong)val); + + return true; + } + + return false; +} + +static void riscv_cpu_register_csr_qtest_callback(void) +{ + static GOnce once; + g_once(&once, (GThreadFunc)qtest_set_command_cb, csr_qtest_callback); +} +#endif + static bool riscv_hart_realize(RISCVHartArrayState *s, int idx, char *cpu_type, Error **errp) { @@ -59,6 +110,10 @@ static void riscv_harts_realize(DeviceState *dev, Error= **errp) =20 s->harts =3D g_new0(RISCVCPU, s->num_harts); =20 +#ifndef CONFIG_USER_ONLY + riscv_cpu_register_csr_qtest_callback(); +#endif + for (n =3D 0; n < s->num_harts; n++) { if (!riscv_hart_realize(s, n, s->cpu_type, errp)) { return; diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c index 817fd7aac5..43bfa496e9 100644 --- a/tests/qtest/libqtest.c +++ b/tests/qtest/libqtest.c @@ -1202,6 +1202,33 @@ uint64_t qtest_rtas_call(QTestState *s, const char *= name, return 0; } =20 +static void qtest_rsp_csr(QTestState *s, uint64_t *val) +{ + gchar **args; + uint64_t ret; + int rc; + + args =3D qtest_rsp_args(s, 3); + + rc =3D qemu_strtou64(args[1], NULL, 16, &ret); + g_assert(rc =3D=3D 0); + rc =3D qemu_strtou64(args[2], NULL, 16, val); + g_assert(rc =3D=3D 0); + + g_strfreev(args); +} + +uint64_t qtest_csr_call(QTestState *s, const char *name, + uint64_t cpu, int csr, + uint64_t *val) +{ + qtest_sendf(s, "csr %s 0x%"PRIx64" %d 0x%"PRIx64"\n", + name, cpu, csr, *val); + + qtest_rsp_csr(s, val); + return 0; +} + void qtest_add_func(const char *str, void (*fn)(void)) { gchar *path =3D g_strdup_printf("/%s/%s", qtest_get_arch(), str); diff --git a/tests/qtest/libqtest.h b/tests/qtest/libqtest.h index beb96b18eb..b516a16bd4 100644 --- a/tests/qtest/libqtest.h +++ b/tests/qtest/libqtest.h @@ -575,6 +575,20 @@ uint64_t qtest_rtas_call(QTestState *s, const char *na= me, uint32_t nargs, uint64_t args, uint32_t nret, uint64_t ret); =20 +/** + * qtest_csr_call: + * @s: #QTestState instance to operate on. + * @name: name of the command to call. + * @cpu: hart number. + * @csr: CSR number. + * @val: Value for reading/writing. + * + * Call an RISC-V CSR read/write function + */ +uint64_t qtest_csr_call(QTestState *s, const char *name, + uint64_t cpu, int csr, + unsigned long *val); + /** * qtest_bufread: * @s: #QTestState instance to operate on. --=20 2.34.1 From nobody Sat Nov 23 15:33:05 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1732087785168571.3561269640788; Tue, 19 Nov 2024 23:29:45 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tDf7t-00022F-4c; Wed, 20 Nov 2024 02:27:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tDf7p-00020N-4c; Wed, 20 Nov 2024 02:27:45 -0500 Received: from mta-03.yadro.com ([89.207.88.253]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tDf7m-000815-Cg; Wed, 20 Nov 2024 02:27:44 -0500 DKIM-Filter: OpenDKIM Filter v2.11.0 mta-03.yadro.com 27FCFE0004 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=syntacore.com; s=mta-04; t=1732087658; bh=wmeSqoVGvMzlf402PU8ZusnH/EFnjksm9+MU6IqoiHc=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type:From; b=Qk/ZT3B4IgbzDFSUwWBBTlZzy1mgIvc9iFwVBN9yavgpF+TDepSjmf/0iDnE/qA3H ajeyY3Boh+FDx5w8dBr6psOlMngVB5YuGuif2VQMr4TRaXtttz+Iu+0EIrx1xPagYJ bUoDQ6vRshyKVTFozkD1jfsgbcgOF5NR32fFdQGCbyLgdhUzrymwJU0/+uJf+YPcN+ 40sEJkVezS0G7Xbcp33Jo5vg4E9fdrP5dRpndv4cUF0YmwA9j3nhLz/kplShxfAj1I PaIuLV+NlNwslqZBwWFMFhPVJ3wH4wLRTHuo2pXnhPCSDgWXtP1YDBzr2VoDCmcHiv w41uwG9peDY8A== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=syntacore.com; s=mta-03; t=1732087658; bh=wmeSqoVGvMzlf402PU8ZusnH/EFnjksm9+MU6IqoiHc=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type:From; b=ucn3qoFMcIXY7uqWUvEoBLlWcNdqgEBPSJcBN5i6JYKm5PFkAZdKbfTlAidXJp1X2 9+J+BFd9VtVxvqN7XPoomsfqmdESnW1i9caDUzS9CW1W4LLD2MrvMhYgRPrJjK1voh SCXPIewLfbgxjBjpgIgr6/bRVf1B2G5dW8L/ZAwda4zgLoNLn6Veqdf6F5Rs0C17Gn i/c2K2b7fcarbp1lwn9dg4jLv5iUXiHpas7NFc9cIjCBN+lW3uFVT/V6eppgsHz/OW 1bpNcu0OCiLdBHfK5EFf+Qo8QSxduet6yLnETralRIgFqoj1QSATJVZSnushIdG/RD GCii7DAn3PrSA== From: Ivan Klokov To: CC: , , , , , , , , , , Ivan Klokov Subject: [RFC PATCH v7 2/2] tests/qtest: QTest example for RISC-V CSR register Date: Wed, 20 Nov 2024 10:27:12 +0300 Message-ID: <20241120072712.65302-3-ivan.klokov@syntacore.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241120072712.65302-1-ivan.klokov@syntacore.com> References: <20241120072712.65302-1-ivan.klokov@syntacore.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: T-EXCH-10.corp.yadro.com (172.17.11.60) To S-Exch-01.corp.yadro.com (10.78.5.241) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=89.207.88.253; envelope-from=ivan.klokov@syntacore.com; helo=mta-03.yadro.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, T_SPF_PERMERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @syntacore.com) (identity @syntacore.com) X-ZM-MESSAGEID: 1732087786705116600 Content-Type: text/plain; charset="utf-8" Added demo for reading CSR register from qtest environment. Signed-off-by: Ivan Klokov Reviewed-by: Fabiano Rosas Reviewed-by: Daniel Henrique Barboza --- tests/qtest/meson.build | 2 +- tests/qtest/riscv-csr-test.c | 56 ++++++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+), 1 deletion(-) create mode 100644 tests/qtest/riscv-csr-test.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index f2f35367ae..3aad77b3a9 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -272,7 +272,7 @@ qtests_s390x =3D \ qtests_riscv32 =3D \ (config_all_devices.has_key('CONFIG_SIFIVE_E_AON') ? ['sifive-e-aon-watc= hdog-test'] : []) =20 -qtests_riscv64 =3D \ +qtests_riscv64 =3D ['riscv-csr-test'] + \ (unpack_edk2_blobs ? ['bios-tables-test'] : []) =20 qos_test_ss =3D ss.source_set() diff --git a/tests/qtest/riscv-csr-test.c b/tests/qtest/riscv-csr-test.c new file mode 100644 index 0000000000..ff5c29e6c6 --- /dev/null +++ b/tests/qtest/riscv-csr-test.c @@ -0,0 +1,56 @@ +/* + * QTest testcase for RISC-V CSRs + * + * Copyright (c) 2024 Syntacore. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "libqtest.h" + +#define CSR_MVENDORID 0xf11 +#define CSR_MISELECT 0x350 + +static void run_test_csr(void) +{ + uint64_t res; + uint64_t val =3D 0; + + QTestState *qts =3D qtest_init("-machine virt -cpu veyron-v1"); + + res =3D qtest_csr_call(qts, "get_csr", 0, CSR_MVENDORID, &val); + + g_assert_cmpint(res, =3D=3D, 0); + g_assert_cmpint(val, =3D=3D, 0x61f); + + val =3D 0xff; + res =3D qtest_csr_call(qts, "set_csr", 0, CSR_MISELECT, &val); + + g_assert_cmpint(res, =3D=3D, 0); + + val =3D 0; + res =3D qtest_csr_call(qts, "get_csr", 0, CSR_MISELECT, &val); + + g_assert_cmpint(res, =3D=3D, 0); + g_assert_cmpint(val, =3D=3D, 0xff); + + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/cpu/csr", run_test_csr); + + return g_test_run(); +} --=20 2.34.1