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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dac21a15sm193049985e9.38.2024.11.19.06.23.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2024 06:23:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732026207; x=1732631007; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=BhPiVkPcywCEaevmfBnlQ6/FILPwbJv9lkpBnJtBRkM=; b=ZkM6ivYJnDepwEJLak7hjRlLGM7ObDNwhFSnU4iTHpmyF+KYtpFMcAI582JqGqXlnj 4CXbPaLKdpOoY5FbAHMLlb1NIZgfbXDMrH6xmkqVRNj19UvpAfU2itHYGFgz8pv/dNF1 WLVv0RJbLu0G/SAVbkO2G2GKKyt+cGkmk/2lJA65abKNKV6hHdB2Cnc91nBV7p5oCW2c sNjPwlA/1PXYc/DWNT9kjwuhY9x8mmmG2JJhqHQpCtORgDsJlaFcEilprsFkYV+9A6Us gRe0WrsfrF2FgnlSJgLu4cL54QywFvCIshGdplW44Eg8r+BUQjzYXfC1GA5uyTfPhcfQ MkXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732026207; x=1732631007; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BhPiVkPcywCEaevmfBnlQ6/FILPwbJv9lkpBnJtBRkM=; b=KCzCKx4sAFBumxrcjLzVrGuS1nUfQ2remxAGvNiXVbKq+Unilx/CEZpic/wLKTS2A2 bI1A4O1Eyfk3BVKRqwMcIe2POrejqzL+PcP8Z5zdCoxMv58MnWkLkK39FExS1cNquU0h 5FmGIpCBxijImZLPJjO5o2/Sl52WBp8p2NNfUW8JXqgFg7wpqetACCJah5iADgehkrK8 j7vrkzgWz0RuLf60GUVHaEn6nOoSfV/8Hx7oYAs/lf+FRLTS5V01C9d4ObkZvIjY6vwn upc7bGNgKAH4xbkGnpsmr4ss1ZO5bFypkkXnjJxXEfLjvf12yBUqEOLoa/Z18UfFPbnf /qbQ== X-Gm-Message-State: AOJu0YxJrdgaua0WTvHQf6AXZDOyOIl+NSRSxjB1XpAeB2TEtaLSaSo6 Dx8dR2vWMmLRVRXIWx50KP0B8bak4mXa0AOnyCTxwJX31hUUUwvR4n7MpvWKzvbXHWrfWYYw4vJ Q X-Google-Smtp-Source: AGHT+IHMCqTS8xOnUnC8urUDCN0dQVgtvcTj+i0FaFOPpLyDrJFmq68hpgS/YVyNSngsJ5I4Qa2TSg== X-Received: by 2002:a05:600c:a06:b0:431:44fe:fd9a with SMTP id 5b1f17b1804b1-432df74ebdcmr139355295e9.19.1732026206986; Tue, 19 Nov 2024 06:23:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/15] arm/ptw: Make get_S1prot accept decoded AP Date: Tue, 19 Nov 2024 14:23:14 +0000 Message-Id: <20241119142321.1853732-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241119142321.1853732-1-peter.maydell@linaro.org> References: <20241119142321.1853732-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1732026380232116600 Content-Type: text/plain; charset="utf-8" From: Pavel Skripkin AP in armv7 short descriptor mode has 3 bits and also domain, which makes it incompatible with other arm schemas. To make it possible to share get_S1prot between armv8, armv7 long format, armv7 short format and armv6 it's easier to make caller decode AP. Signed-off-by: Pavel Skripkin Message-id: 20241118152526.45185-1-paskripkin@gmail.com [PMM: fixed checkpatch nit] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/ptw.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 98499495085..b132910c401 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1357,25 +1357,24 @@ static int get_S2prot(CPUARMState *env, int s2ap, i= nt xn, bool s1_is_el0) * @env: CPUARMState * @mmu_idx: MMU index indicating required translation regime * @is_aa64: TRUE if AArch64 - * @ap: The 2-bit simple AP (AP[2:1]) + * @user_rw: Translated AP for user access + * @prot_rw: Translated AP for privileged access * @xn: XN (execute-never) bit * @pxn: PXN (privileged execute-never) bit * @in_pa: The original input pa space * @out_pa: The output pa space, modified by NSTable, NS, and NSE */ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, - int ap, int xn, int pxn, + int user_rw, int prot_rw, int xn, int pxn, ARMSecuritySpace in_pa, ARMSecuritySpace out_pa) { ARMCPU *cpu =3D env_archcpu(env); bool is_user =3D regime_is_user(env, mmu_idx); - int prot_rw, user_rw; bool have_wxn; int wxn =3D 0; =20 assert(!regime_is_stage2(mmu_idx)); =20 - user_rw =3D simple_ap_to_rw_prot_is_user(ap, true); if (is_user) { prot_rw =3D user_rw; } else { @@ -1393,8 +1392,6 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu= _idx, bool is_aa64, regime_is_pan(env, mmu_idx) && (regime_sctlr(env, mmu_idx) & SCTLR_EPAN) && !xn) { prot_rw =3D 0; - } else { - prot_rw =3D simple_ap_to_rw_prot_is_user(ap, false); } } =20 @@ -2044,6 +2041,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, int nse, ns =3D extract32(attrs, 5, 1); uint8_t attrindx; uint64_t mair; + int user_rw, prot_rw; =20 switch (out_space) { case ARMSS_Root: @@ -2110,12 +2108,15 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, xn =3D 0; ap &=3D ~1; } + + user_rw =3D simple_ap_to_rw_prot_is_user(ap, true); + prot_rw =3D simple_ap_to_rw_prot_is_user(ap, false); /* * Note that we modified ptw->in_space earlier for NSTable, but * result->f.attrs retains a copy of the original security space. */ - result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, ap, xn, pxn, - result->f.attrs.space, out_space); + result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, user_rw, prot= _rw, + xn, pxn, result->f.attrs.space, out_sp= ace); =20 /* Index into MAIR registers for cache attributes */ attrindx =3D extract32(attrs, 2, 3); --=20 2.34.1