From nobody Sat Nov 23 20:45:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1732026434; cv=none; d=zohomail.com; s=zohoarc; b=O0NEwpoSKyaJkbnXPvQPEsOkxaUoM1HBWljpB9Yewvdc1/tlx6GI148HtqTgGQHyNPeXG/+kYjRRh5J8YCDNVygxuEGQVyUKcZzPrMkrvxG3GiIuYT5DwzDUCoAg+3ksWic1x1vS/OOnlvaMgOd/Bh4QSeQmQ4jYLiSXQ6BqVMw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1732026434; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Sdn+fHZSuW869Y/sZVE+aCL+8h470EXCSMBPbW6o5fA=; b=gQW9oMvQAVoS30iWK0cRvcgOdTNWKIMrj7EBo1H4fsv8NhJ6wTv7T6wxSf5tv/TZbRjAwXJ4XYS+ZAzgLPHGEkSRDF2JidJ+CASY/YCaUw+7ZMnNCoBPzSURV9VaWWpJg9IkI0L2lVp9p6/GBzqhVsM+/UexrNqnYE0yRD4it2U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1732026434452806.9054693475755; Tue, 19 Nov 2024 06:27:14 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tDP8h-0005vt-71; Tue, 19 Nov 2024 09:23:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tDP8c-0005sj-Ci for qemu-devel@nongnu.org; Tue, 19 Nov 2024 09:23:30 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tDP8a-0006D1-2l for qemu-devel@nongnu.org; Tue, 19 Nov 2024 09:23:30 -0500 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-43158625112so30503295e9.3 for ; Tue, 19 Nov 2024 06:23:27 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-432dac21a15sm193049985e9.38.2024.11.19.06.23.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Nov 2024 06:23:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1732026206; x=1732631006; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Sdn+fHZSuW869Y/sZVE+aCL+8h470EXCSMBPbW6o5fA=; b=Axo7xINgEzl/1c6O2bU/HxBLKiU9/VM2rVzreNSOZFIxeNBCjQF2tXrC04WJJY7IqQ cxt4eW54hYfQGDc9yeC/wCpMOadcIMR5DOeQirx4Jg1PUyQpVhs/eSRF3BVNJ7M6GlCh uujGR3UQDYSwE2tyHbw0DpOG2yX9GnexE2TgslOQdAZx8glmu1a7Kl4ElKNy4zK/nEw/ NUIjf0PQgNB55+75+Q2x+POWhetWp1H21RMU8TuPr662ELlKLwmgDX6Eec2vrhNdjRue 2XhCzu5nvrBWzzW1tnfw7X9+7uPS6JnBRAH3Z+YKcZv3j/WzeiVMvAm4hw6G8sa0Dc5z mgUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732026206; x=1732631006; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Sdn+fHZSuW869Y/sZVE+aCL+8h470EXCSMBPbW6o5fA=; b=MQVJgGloN/MSgxtXU7PlAb8qXFAdZrMloJakFzHiVPmE57AIlZHnLS0YDx9DfLb+3+ 6qMeDW4H8AoItgggo6Mc7fpv0OkTJvZVQSP8UQdhHOJHCnpq0ULmeNYWb7B9GaB+wG0V p0gaqCzzm+FB7SgbWXZ6PhYOiwaGZTQmiPN0RVIIhPfnpWURv7gAVbF6m+QCp7QLbbHx B5OhlvZJyY2SM3tnCWmyQRwL/Srf2kRZuvB3vrAEDuX7XOnzI3gids2DuGP9etltCEvp r9NReOF1KpCfXHAQ1fyDZ2GTIW+dfhODSo2ITCn7M3aikZcgyBPciW3UDAQ0R34lFTOh Ld0Q== X-Gm-Message-State: AOJu0Yz0ANcGDGeKCsmMZzJI/HUS3xRygAvBiCoM+Cjx2btMq9cJ3URS yHoBONi8LVn00g57adnbj5N3fzR4UUNWnDJETifzKxvu2SDDJAvqH9I6fPLJunhGvH7MUgvzYIG A X-Google-Smtp-Source: AGHT+IGMW1NWkZpZx/bm22TpGK3J4Bn4HejKt7cIh4dy6NenDlv3KFx1pXA/oBikVMci33agj9jVCw== X-Received: by 2002:a05:600c:5487:b0:431:44fe:fd9f with SMTP id 5b1f17b1804b1-432df78a529mr120535315e9.23.1732026206495; Tue, 19 Nov 2024 06:23:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/15] tests/qtest/cmsdk-apb-watchdog-test: Test INTEN as counter enable Date: Tue, 19 Nov 2024 14:23:13 +0000 Message-Id: <20241119142321.1853732-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241119142321.1853732-1-peter.maydell@linaro.org> References: <20241119142321.1853732-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1732026436715116600 Content-Type: text/plain; charset="utf-8" From: Roque Arcudia Hernandez The following tests focus on making sure the counter is not running out of reset and the proper use of INTEN as the counter enable. As described in: https://developer.arm.com/documentation/ddi0479/d/apb-components/apb-watchd= og/programmers-model The new tests have to target an MPS2 machine because the original machine used by the test (stellaris) has a variation of the cmsdk_apb_watchdog that locks INTEN when it is programmed to 1. The stellaris machine also does not reproduce the problem of the counter running out of cold reset due to the way the clocks are initialized. Signed-off-by: Roque Arcudia Hernandez Reviewed-by: Stephen Longfield Message-id: 20241115160328.1650269-6-roqueh@google.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- tests/qtest/cmsdk-apb-watchdog-test.c | 215 ++++++++++++++++++++++++++ 1 file changed, 215 insertions(+) diff --git a/tests/qtest/cmsdk-apb-watchdog-test.c b/tests/qtest/cmsdk-apb-= watchdog-test.c index fe535a553cc..53538f98c99 100644 --- a/tests/qtest/cmsdk-apb-watchdog-test.c +++ b/tests/qtest/cmsdk-apb-watchdog-test.c @@ -68,6 +68,16 @@ static const CMSDKAPBWatchdogTestArgs machine_info[] =3D= { }, }; =20 +static void system_reset(QTestState *qtest) +{ + QDict *resp; + + resp =3D qtest_qmp(qtest, "{'execute': 'system_reset'}"); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); + qtest_qmp_eventwait(qtest, "RESET"); +} + static void test_watchdog(const void *ptr) { const CMSDKAPBWatchdogTestArgs *args =3D ptr; @@ -159,6 +169,199 @@ static void test_clock_change(const void *ptr) qtest_end(); } =20 +/* Tests the counter is not running after reset. */ +static void test_watchdog_reset(const void *ptr) +{ + const CMSDKAPBWatchdogTestArgs *args =3D ptr; + hwaddr wdog_base =3D args->wdog_base; + int64_t tick =3D args->tick; + g_autofree gchar *cmdline =3D g_strdup_printf("-machine %s", args->mac= hine); + qtest_start(cmdline); + g_assert_cmpuint(readl(wdog_base + WDOGRIS), =3D=3D, 0); + + g_assert_cmphex(readl(wdog_base + WDOGLOAD), =3D=3D, WDOGLOAD_DEFAULT); + g_assert_cmphex(readl(wdog_base + WDOGVALUE), =3D=3D, WDOGVALUE_DEFAUL= T); + + g_assert_cmphex(readl(wdog_base + WDOGCONTROL), =3D=3D, 0); + + /* + * The counter should not be running if WDOGCONTROL.INTEN has not been= set, + * as it is the case after a cold reset. + */ + clock_step(15 * tick + 1); + g_assert_cmphex(readl(wdog_base + WDOGLOAD), =3D=3D, WDOGLOAD_DEFAULT); + g_assert_cmphex(readl(wdog_base + WDOGVALUE), =3D=3D, WDOGVALUE_DEFAUL= T); + + /* Let the counter run before reset */ + writel(wdog_base + WDOGLOAD, 3000); + writel(wdog_base + WDOGCONTROL, 1); + + /* Verify it is running */ + clock_step(1000 * tick + 1); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 3000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 2000); + + system_reset(global_qtest); + + /* Check defaults after reset */ + g_assert_cmphex(readl(wdog_base + WDOGLOAD), =3D=3D, WDOGLOAD_DEFAULT); + g_assert_cmphex(readl(wdog_base + WDOGVALUE), =3D=3D, WDOGVALUE_DEFAUL= T); + + /* The counter should not be running after reset. */ + clock_step(1000 * tick + 1); + g_assert_cmphex(readl(wdog_base + WDOGLOAD), =3D=3D, WDOGLOAD_DEFAULT); + g_assert_cmphex(readl(wdog_base + WDOGVALUE), =3D=3D, WDOGVALUE_DEFAUL= T); + + qtest_end(); +} + +/* + * Tests inten works as the counter enable based on this description: + * + * Enable the interrupt event, WDOGINT. Set HIGH to enable the counter and= the + * interrupt, or LOW to disable the counter and interrupt. Reloads the cou= nter + * from the value in WDOGLOAD when the interrupt is enabled, after previou= sly + * being disabled. + */ +static void test_watchdog_inten(const void *ptr) +{ + const CMSDKAPBWatchdogTestArgs *args =3D ptr; + hwaddr wdog_base =3D args->wdog_base; + int64_t tick =3D args->tick; + g_autofree gchar *cmdline =3D g_strdup_printf("-machine %s", args->mac= hine); + qtest_start(cmdline); + g_assert_cmpuint(readl(wdog_base + WDOGRIS), =3D=3D, 0); + + g_assert_cmphex(readl(wdog_base + WDOGLOAD), =3D=3D, WDOGLOAD_DEFAULT); + g_assert_cmphex(readl(wdog_base + WDOGVALUE), =3D=3D, WDOGVALUE_DEFAUL= T); + + /* + * When WDOGLOAD is written to, the count is immediately restarted fro= m the + * new value. + * + * Note: the counter should not be running as long as WDOGCONTROL.INTE= N is + * not set + */ + writel(wdog_base + WDOGLOAD, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 4000); + clock_step(500 * tick + 1); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 4000); + + /* Set HIGH WDOGCONTROL.INTEN to enable the counter and the interrupt = */ + writel(wdog_base + WDOGCONTROL, 1); + clock_step(500 * tick + 1); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 3500); + + /* or LOW to disable the counter and interrupt. */ + writel(wdog_base + WDOGCONTROL, 0); + clock_step(100 * tick); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 3500); + + /* + * Reloads the counter from the value in WDOGLOAD when the interrupt is + * enabled, after previously being disabled. + */ + writel(wdog_base + WDOGCONTROL, 1); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 4000); + + /* Test counter is still on */ + clock_step(50 * tick + 1); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 3950); + + /* + * When WDOGLOAD is written to, the count is immediately restarted fro= m the + * new value. + * + * Note: the counter should be running since WDOGCONTROL.INTEN is set + */ + writel(wdog_base + WDOGLOAD, 5000); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 5000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 5000); + clock_step(4999 * tick + 1); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 5000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 1); + g_assert_cmpuint(readl(wdog_base + WDOGRIS), =3D=3D, 0); + + /* Finally disable and check the conditions don't change */ + writel(wdog_base + WDOGCONTROL, 0); + clock_step(10 * tick); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 5000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 1); + g_assert_cmpuint(readl(wdog_base + WDOGRIS), =3D=3D, 0); + + qtest_end(); +} + +/* + * Tests the following custom behavior: + * + * The Luminary version of this device ignores writes to this register aft= er the + * guest has enabled interrupts (so they can only be disabled again via re= set). + */ +static void test_watchdog_inten_luminary(const void *ptr) +{ + const CMSDKAPBWatchdogTestArgs *args =3D ptr; + hwaddr wdog_base =3D args->wdog_base; + int64_t tick =3D args->tick; + g_autofree gchar *cmdline =3D g_strdup_printf("-machine %s", args->mac= hine); + qtest_start(cmdline); + g_assert_cmpuint(readl(wdog_base + WDOGRIS), =3D=3D, 0); + + g_assert_cmphex(readl(wdog_base + WDOGLOAD), =3D=3D, WDOGLOAD_DEFAULT); + g_assert_cmphex(readl(wdog_base + WDOGVALUE), =3D=3D, WDOGVALUE_DEFAUL= T); + + /* + * When WDOGLOAD is written to, the count is immediately restarted fro= m the + * new value. + * + * Note: the counter should not be running as long as WDOGCONTROL.INTE= N is + * not set + */ + writel(wdog_base + WDOGLOAD, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 4000); + clock_step(500 * tick + 1); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 4000); + + /* Set HIGH WDOGCONTROL.INTEN to enable the counter and the interrupt = */ + writel(wdog_base + WDOGCONTROL, 1); + clock_step(500 * tick + 1); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 3500); + + /* + * The Luminary version of this device ignores writes to this register= after + * the guest has enabled interrupts + */ + writel(wdog_base + WDOGCONTROL, 0); + clock_step(100 * tick); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 3400); + g_assert_cmphex(readl(wdog_base + WDOGCONTROL), =3D=3D, 0x1); + + /* They can only be disabled again via reset */ + system_reset(global_qtest); + + /* Check defaults after reset */ + g_assert_cmphex(readl(wdog_base + WDOGLOAD), =3D=3D, WDOGLOAD_DEFAULT); + g_assert_cmphex(readl(wdog_base + WDOGVALUE), =3D=3D, WDOGVALUE_DEFAUL= T); + g_assert_cmphex(readl(wdog_base + WDOGCONTROL), =3D=3D, 0); + + /* The counter should not be running after reset. */ + clock_step(1000 * tick + 1); + g_assert_cmphex(readl(wdog_base + WDOGLOAD), =3D=3D, WDOGLOAD_DEFAULT); + g_assert_cmphex(readl(wdog_base + WDOGVALUE), =3D=3D, WDOGVALUE_DEFAUL= T); + + qtest_end(); +} + int main(int argc, char **argv) { int r; @@ -172,10 +375,22 @@ int main(int argc, char **argv) qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_clock_change", &machine_info[MACHINE_LM3S811EVB], test_clock_change); + qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_reset", + &machine_info[MACHINE_LM3S811EVB], + test_watchdog_reset); + qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_inten_luminary", + &machine_info[MACHINE_LM3S811EVB], + test_watchdog_inten_luminary); } if (qtest_has_machine(machine_info[MACHINE_MPS2_AN385].machine)) { qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_mps2", &machine_info[MACHINE_MPS2_AN385], test_watchd= og); + qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_reset_mps2", + &machine_info[MACHINE_MPS2_AN385], + test_watchdog_reset); + qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_inten", + &machine_info[MACHINE_MPS2_AN385], + test_watchdog_inten); } =20 r =3D g_test_run(); --=20 2.34.1