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Sun, 17 Nov 2024 17:16:55 -0800 (PST) From: Atish Patra Date: Sun, 17 Nov 2024 17:15:51 -0800 Subject: [PATCH v3 03/11] target/riscv: Enable S*stateen bits for AIA MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241117-counter_delegation-v3-3-476d6f36e3c8@rivosinc.com> References: <20241117-counter_delegation-v3-0-476d6f36e3c8@rivosinc.com> In-Reply-To: <20241117-counter_delegation-v3-0-476d6f36e3c8@rivosinc.com> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: kaiwenxue1@gmail.com, Atish Patra , palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, alistair.francis@wdc.com X-Mailer: b4 0.15-dev-13183 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=atishp@rivosinc.com; helo=mail-pf1-x436.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1731892757728116600 As per the ratified AIA spec v1.0, three stateen bits control AIA CSR access. Bit 60 controls the indirect CSRs Bit 59 controls the most AIA CSR state Bit 58 controls the IMSIC state such as stopei and vstopei Enable the corresponding bits in [m|h]stateen and enable corresponding checks in the CSR accessor functions. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/csr.c | 85 ++++++++++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 84 insertions(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 52e0139fc99c..c91a26a52ef6 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -335,19 +335,42 @@ static RISCVException smode32(CPURISCVState *env, int= csrno) =20 static RISCVException aia_smode(CPURISCVState *env, int csrno) { + int ret; + if (!riscv_cpu_cfg(env)->ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 + if (csrno =3D=3D CSR_STOPEI) { + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_IMSIC); + } else { + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_AIA); + } + + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return smode(env, csrno); } =20 static RISCVException aia_smode32(CPURISCVState *env, int csrno) { + int ret; + if (!riscv_cpu_cfg(env)->ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_AIA); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return smode32(env, csrno); } =20 @@ -586,15 +609,38 @@ static RISCVException pointer_masking(CPURISCVState *= env, int csrno) =20 static RISCVException aia_hmode(CPURISCVState *env, int csrno) { + int ret; + if (!riscv_cpu_cfg(env)->ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 - return hmode(env, csrno); + if (csrno =3D=3D CSR_VSTOPEI) { + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_IMSIC); + } else { + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_AIA); + } + + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + + return hmode(env, csrno); } =20 static RISCVException aia_hmode32(CPURISCVState *env, int csrno) { + int ret; + + if (!riscv_cpu_cfg(env)->ext_ssaia) { + return RISCV_EXCP_ILLEGAL_INST; + } + + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_AIA); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + if (!riscv_cpu_cfg(env)->ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } @@ -2030,6 +2076,12 @@ static RISCVException rmw_xiselect(CPURISCVState *en= v, int csrno, target_ulong wr_mask) { target_ulong *iselect; + int ret; + + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } =20 /* Translate CSR number for VS-mode */ csrno =3D csrind_xlate_vs_csrno(env, csrno); @@ -2200,6 +2252,11 @@ static RISCVException rmw_xireg(CPURISCVState *env, = int csrno, int ret =3D -EINVAL; target_ulong isel; =20 + ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + /* Translate CSR number for VS-mode */ csrno =3D csrind_xlate_vs_csrno(env, csrno); =20 @@ -2678,6 +2735,19 @@ static RISCVException write_mstateen0(CPURISCVState = *env, int csrno, wr_mask |=3D SMSTATEEN0_P1P13; } =20 + if (riscv_cpu_cfg(env)->ext_smaia) { + wr_mask |=3D SMSTATEEN0_SVSLCT; + } + + /* + * As per the AIA specification, SMSTATEEN0_IMSIC is valid only if IMS= IC is + * implemented. However, that information is with MachineState and we = can't + * figure that out in csr.c. Just enable if Smaia is available. + */ + if (riscv_cpu_cfg(env)->ext_smaia) { + wr_mask |=3D (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC); + } + return write_mstateen(env, csrno, wr_mask, new_val); } =20 @@ -2758,6 +2828,19 @@ static RISCVException write_hstateen0(CPURISCVState = *env, int csrno, wr_mask |=3D SMSTATEEN0_FCSR; } =20 + if (riscv_cpu_cfg(env)->ext_ssaia) { + wr_mask |=3D SMSTATEEN0_SVSLCT; + } + + /* + * As per the AIA specification, SMSTATEEN0_IMSIC is valid only if IMS= IC is + * implemented. However, that information is with MachineState and we = can't + * figure that out in csr.c. Just enable if Ssaia is available. + */ + if (riscv_cpu_cfg(env)->ext_ssaia) { + wr_mask |=3D (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC); + } + return write_hstateen(env, csrno, wr_mask, new_val); } =20 --=20 2.34.1