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Sun, 17 Nov 2024 17:16:54 -0800 (PST) From: Atish Patra Date: Sun, 17 Nov 2024 17:15:50 -0800 Subject: [PATCH v3 02/11] target/riscv: Decouple AIA processing from xiselect and xireg MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20241117-counter_delegation-v3-2-476d6f36e3c8@rivosinc.com> References: <20241117-counter_delegation-v3-0-476d6f36e3c8@rivosinc.com> In-Reply-To: <20241117-counter_delegation-v3-0-476d6f36e3c8@rivosinc.com> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: kaiwenxue1@gmail.com, Atish Patra , palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, alistair.francis@wdc.com, Kaiwen Xue X-Mailer: b4 0.15-dev-13183 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=atishp@rivosinc.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1731892721696116600 From: Kaiwen Xue Since xiselect and xireg also will be of use in sxcsrind, AIA should have its own separated interface when those CSRs are accessed. Signed-off-by: Kaiwen Xue Reviewed-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/csr.c | 165 ++++++++++++++++++++++++++++++++++++++++++++-----= ---- 1 file changed, 139 insertions(+), 26 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9846770820f4..52e0139fc99c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -29,6 +29,7 @@ #include "sysemu/cpu-timers.h" #include "qemu/guest-random.h" #include "qapi/error.h" +#include =20 /* CSR function table public API */ void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) @@ -305,6 +306,15 @@ static RISCVException aia_any32(CPURISCVState *env, in= t csrno) return any32(env, csrno); } =20 +static RISCVException csrind_or_aia_any(CPURISCVState *env, int csrno) +{ + if (!riscv_cpu_cfg(env)->ext_smaia && !riscv_cpu_cfg(env)->ext_smcsrin= d) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return any(env, csrno); +} + static RISCVException smode(CPURISCVState *env, int csrno) { if (riscv_has_ext(env, RVS)) { @@ -341,6 +351,30 @@ static RISCVException aia_smode32(CPURISCVState *env, = int csrno) return smode32(env, csrno); } =20 +static bool csrind_extensions_present(CPURISCVState *env) +{ + return riscv_cpu_cfg(env)->ext_smcsrind || riscv_cpu_cfg(env)->ext_ssc= srind; +} + +static bool aia_extensions_present(CPURISCVState *env) +{ + return riscv_cpu_cfg(env)->ext_smaia || riscv_cpu_cfg(env)->ext_ssaia; +} + +static bool csrind_or_aia_extensions_present(CPURISCVState *env) +{ + return csrind_extensions_present(env) || aia_extensions_present(env); +} + +static RISCVException csrind_or_aia_smode(CPURISCVState *env, int csrno) +{ + if (!csrind_or_aia_extensions_present(env)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return smode(env, csrno); +} + static RISCVException hmode(CPURISCVState *env, int csrno) { if (riscv_has_ext(env, RVH)) { @@ -360,6 +394,15 @@ static RISCVException hmode32(CPURISCVState *env, int = csrno) =20 } =20 +static RISCVException csrind_or_aia_hmode(CPURISCVState *env, int csrno) +{ + if (!csrind_or_aia_extensions_present(env)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return hmode(env, csrno); +} + static RISCVException umode(CPURISCVState *env, int csrno) { if (riscv_has_ext(env, RVU)) { @@ -1966,6 +2009,22 @@ static int aia_xlate_vs_csrno(CPURISCVState *env, in= t csrno) }; } =20 +static int csrind_xlate_vs_csrno(CPURISCVState *env, int csrno) +{ + if (!env->virt_enabled) { + return csrno; + } + + switch (csrno) { + case CSR_SISELECT: + return CSR_VSISELECT; + case CSR_SIREG: + return CSR_VSIREG; + default: + return csrno; + }; +} + static RISCVException rmw_xiselect(CPURISCVState *env, int csrno, target_ulong *val, target_ulong new_val, target_ulong wr_mask) @@ -1973,7 +2032,7 @@ static RISCVException rmw_xiselect(CPURISCVState *env= , int csrno, target_ulong *iselect; =20 /* Translate CSR number for VS-mode */ - csrno =3D aia_xlate_vs_csrno(env, csrno); + csrno =3D csrind_xlate_vs_csrno(env, csrno); =20 /* Find the iselect CSR based on CSR number */ switch (csrno) { @@ -2002,6 +2061,12 @@ static RISCVException rmw_xiselect(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } =20 +static bool xiselect_aia_range(target_ulong isel) +{ + return (ISELECT_IPRIO0 <=3D isel && isel <=3D ISELECT_IPRIO15) || + (ISELECT_IMSIC_FIRST <=3D isel && isel <=3D ISELECT_IMSIC_LAST); +} + static int rmw_iprio(target_ulong xlen, target_ulong iselect, uint8_t *iprio, target_ulong *val, target_ulong new_val, @@ -2047,45 +2112,44 @@ static int rmw_iprio(target_ulong xlen, return 0; } =20 -static RISCVException rmw_xireg(CPURISCVState *env, int csrno, - target_ulong *val, target_ulong new_val, - target_ulong wr_mask) +static RISCVException rmw_xireg_aia(CPURISCVState *env, int csrno, + target_ulong isel, target_ulong *val, + target_ulong new_val, target_ulong wr_mask) { - bool virt, isel_reserved; - uint8_t *iprio; + bool virt =3D false, isel_reserved =3D false; int ret =3D -EINVAL; - target_ulong priv, isel, vgein; - - /* Translate CSR number for VS-mode */ - csrno =3D aia_xlate_vs_csrno(env, csrno); + uint8_t *iprio; + target_ulong priv, vgein; =20 - /* Decode register details from CSR number */ - virt =3D false; - isel_reserved =3D false; + /* VS-mode CSR number passed in has already been translated */ switch (csrno) { case CSR_MIREG: + if (!riscv_cpu_cfg(env)->ext_smaia) { + goto done; + } iprio =3D env->miprio; - isel =3D env->miselect; priv =3D PRV_M; break; case CSR_SIREG: - if (env->priv =3D=3D PRV_S && env->mvien & MIP_SEIP && + if (!riscv_cpu_cfg(env)->ext_ssaia || + (env->priv =3D=3D PRV_S && env->mvien & MIP_SEIP && env->siselect >=3D ISELECT_IMSIC_EIDELIVERY && - env->siselect <=3D ISELECT_IMSIC_EIE63) { + env->siselect <=3D ISELECT_IMSIC_EIE63)) { goto done; } iprio =3D env->siprio; - isel =3D env->siselect; priv =3D PRV_S; break; case CSR_VSIREG: + if (!riscv_cpu_cfg(env)->ext_ssaia) { + goto done; + } iprio =3D env->hviprio; - isel =3D env->vsiselect; priv =3D PRV_S; virt =3D true; break; default: - goto done; + goto done; }; =20 /* Find the selected guest interrupt file */ @@ -2116,10 +2180,54 @@ static RISCVException rmw_xireg(CPURISCVState *env,= int csrno, } =20 done: + /* + * If AIA is not enabled, illegal instruction exception is always + * returned regardless of whether we are in VS-mode or not + */ if (ret) { return (env->virt_enabled && virt && !isel_reserved) ? RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; } + + return RISCV_EXCP_NONE; +} + +static RISCVException rmw_xireg(CPURISCVState *env, int csrno, + target_ulong *val, target_ulong new_val, + target_ulong wr_mask) +{ + bool virt =3D false; + int ret =3D -EINVAL; + target_ulong isel; + + /* Translate CSR number for VS-mode */ + csrno =3D csrind_xlate_vs_csrno(env, csrno); + + /* Decode register details from CSR number */ + switch (csrno) { + case CSR_MIREG: + isel =3D env->miselect; + break; + case CSR_SIREG: + isel =3D env->siselect; + break; + case CSR_VSIREG: + isel =3D env->vsiselect; + virt =3D true; + break; + default: + goto done; + }; + + if (xiselect_aia_range(isel)) { + return rmw_xireg_aia(env, csrno, isel, val, new_val, wr_mask); + } + +done: + if (ret) { + return (env->virt_enabled && virt) ? + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; + } return RISCV_EXCP_NONE; } =20 @@ -5065,8 +5173,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MIP] =3D { "mip", any, NULL, NULL, rmw_mip }, =20 /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ - [CSR_MISELECT] =3D { "miselect", aia_any, NULL, NULL, rmw_xiselec= t }, - [CSR_MIREG] =3D { "mireg", aia_any, NULL, NULL, rmw_xireg }, + [CSR_MISELECT] =3D { "miselect", csrind_or_aia_any, NULL, NULL, + rmw_xiselect }, + [CSR_MIREG] =3D { "mireg", csrind_or_aia_any, NULL, NULL, + rmw_xireg }, =20 /* Machine-Level Interrupts (AIA) */ [CSR_MTOPEI] =3D { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, @@ -5184,8 +5294,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_SATP] =3D { "satp", satp, read_satp, write_satp }, =20 /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ - [CSR_SISELECT] =3D { "siselect", aia_smode, NULL, NULL, rmw_xisele= ct }, - [CSR_SIREG] =3D { "sireg", aia_smode, NULL, NULL, rmw_xireg = }, + [CSR_SISELECT] =3D { "siselect", csrind_or_aia_smode, NULL, NULL, + rmw_xiselect = }, + [CSR_SIREG] =3D { "sireg", csrind_or_aia_smode, NULL, NULL, + rmw_xireg = }, =20 /* Supervisor-Level Interrupts (AIA) */ [CSR_STOPEI] =3D { "stopei", aia_smode, NULL, NULL, rmw_xtopei= }, @@ -5264,9 +5376,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* * VS-Level Window to Indirectly Accessed Registers (H-extension with = AIA) */ - [CSR_VSISELECT] =3D { "vsiselect", aia_hmode, NULL, NULL, - rmw_xiselect = }, - [CSR_VSIREG] =3D { "vsireg", aia_hmode, NULL, NULL, rmw_xire= g }, + [CSR_VSISELECT] =3D { "vsiselect", csrind_or_aia_hmode, NULL, NULL, + rmw_xiselect = }, + [CSR_VSIREG] =3D { "vsireg", csrind_or_aia_hmode, NULL, NULL, + rmw_xireg = }, =20 /* VS-Level Interrupts (H-extension with AIA) */ [CSR_VSTOPEI] =3D { "vstopei", aia_hmode, NULL, NULL, rmw_xtop= ei }, --=20 2.34.1