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Iglesias" , qemu-arm@nongnu.org, Richard Henderson , Thomas Huth , Anton Johansson , Bernhard Beschow , Alistair Francis , Paolo Bonzini , Gustavo Romero , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Peter Maydell , Jason Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH RESEND v2 17/19] hw/net/xilinx_ethlite: Map the RAM buffer as RAM memory region Date: Thu, 14 Nov 2024 22:00:08 +0100 Message-ID: <20241114210010.34502-18-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114210010.34502-1-philmd@linaro.org> References: <20241114210010.34502-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731618185517116600 Rather than using I/O registers for RAM buffer, having to swap endianness back and forth (because the core memory layer automatically swaps endiannes for us), declare the buffers as RAM regions. The "xlnx.xps-ethernetlite" MR doesn't have any more I/O regions. Remove the now unused s->regs[] array. The memory flat view becomes: FlatView #0 Root memory region: system 0000000081000000-00000000810007e3 (prio 0, ram): ethlite.tx[0]buf 00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio 00000000810007f4-00000000810007ff (prio 0, i/o): ethlite.tx[0]io 0000000081000800-0000000081000fe3 (prio 0, ram): ethlite.tx[1]buf 0000000081000ff4-0000000081000fff (prio 0, i/o): ethlite.tx[1]io 0000000081001000-00000000810017e3 (prio 0, ram): ethlite.rx[0]buf 00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io 0000000081001800-0000000081001fe3 (prio 0, ram): ethlite.rx[1]buf 0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io Reported-by: Paolo Bonzini Reviewed-by: Edgar E. Iglesias Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/net/xilinx_ethlite.c | 81 +++++++++-------------------------------- 1 file changed, 17 insertions(+), 64 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index c710857cfd..0d445653b2 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -2,6 +2,7 @@ * QEMU model of the Xilinx Ethernet Lite MAC. * * Copyright (c) 2009 Edgar E. Iglesias. + * Copyright (c) 2024 Linaro, Ltd * * DS580: https://docs.amd.com/v/u/en-US/xps_ethernetlite * LogiCORE IP XPS Ethernet Lite Media Access Controller @@ -30,7 +31,6 @@ #include "qemu/bitops.h" #include "qom/object.h" #include "qapi/error.h" -#include "exec/tswap.h" #include "hw/sysbus.h" #include "hw/irq.h" #include "hw/qdev-properties.h" @@ -38,18 +38,12 @@ #include "net/net.h" #include "trace.h" =20 -#define R_TX_BUF0 0 #define BUFSZ_MAX 0x07e4 #define A_MDIO_BASE 0x07e4 #define A_TX_BASE0 0x07f4 -#define R_TX_BUF1 (0x0800 / 4) #define A_TX_BASE1 0x0ff4 - -#define R_RX_BUF0 (0x1000 / 4) #define A_RX_BASE0 0x17fc -#define R_RX_BUF1 (0x1800 / 4) #define A_RX_BASE1 0x1ffc -#define R_MAX (0x2000 / 4) =20 enum { TX_LEN =3D 0, @@ -73,6 +67,8 @@ typedef struct XlnxXpsEthLitePort { MemoryRegion txio; MemoryRegion rxio; + MemoryRegion txbuf; + MemoryRegion rxbuf; =20 struct { uint32_t tx_len; @@ -101,7 +97,6 @@ struct XlnxXpsEthLite =20 UnimplementedDeviceState mdio; XlnxXpsEthLitePort port[2]; - uint32_t regs[R_MAX]; }; =20 static inline void eth_pulse_irq(XlnxXpsEthLite *s) @@ -119,16 +114,12 @@ static unsigned addr_to_port_index(hwaddr addr) =20 static void *txbuf_ptr(XlnxXpsEthLite *s, unsigned port_index) { - unsigned int rxbase =3D port_index * (0x800 / 4); - - return &s->regs[rxbase + R_TX_BUF0]; + return memory_region_get_ram_ptr(&s->port[port_index].txbuf); } =20 static void *rxbuf_ptr(XlnxXpsEthLite *s, unsigned port_index) { - unsigned int rxbase =3D port_index * (0x800 / 4); - - return &s->regs[rxbase + R_RX_BUF0]; + return memory_region_get_ram_ptr(&s->port[port_index].rxbuf); } =20 static uint64_t port_tx_read(void *opaque, hwaddr addr, unsigned int size) @@ -255,53 +246,6 @@ static const MemoryRegionOps eth_portrx_ops =3D { }, }; =20 -static uint64_t -eth_read(void *opaque, hwaddr addr, unsigned int size) -{ - XlnxXpsEthLite *s =3D opaque; - uint32_t r =3D 0; - - addr >>=3D 2; - - switch (addr) - { - default: - r =3D tswap32(s->regs[addr]); - break; - } - return r; -} - -static void -eth_write(void *opaque, hwaddr addr, - uint64_t val64, unsigned int size) -{ - XlnxXpsEthLite *s =3D opaque; - uint32_t value =3D val64; - - addr >>=3D 2; - switch (addr)=20 - { - default: - s->regs[addr] =3D tswap32(value); - break; - } -} - -static const MemoryRegionOps eth_ops =3D { - .read =3D eth_read, - .write =3D eth_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, - .impl =3D { - .min_access_size =3D 4, - .max_access_size =3D 4, - }, - .valid =3D { - .min_access_size =3D 4, - .max_access_size =3D 4 - } -}; - static bool eth_can_rx(NetClientState *nc) { XlnxXpsEthLite *s =3D qemu_get_nic_opaque(nc); @@ -357,6 +301,9 @@ static void xilinx_ethlite_realize(DeviceState *dev, Er= ror **errp) { XlnxXpsEthLite *s =3D XILINX_ETHLITE(dev); =20 + memory_region_init(&s->mmio, OBJECT(dev), + "xlnx.xps-ethernetlite", 0x2000); + object_initialize_child(OBJECT(dev), "ethlite.mdio", &s->mdio, TYPE_UNIMPLEMENTED_DEVICE); qdev_prop_set_string(DEVICE(&s->mdio), "name", "ethlite.mdio"); @@ -366,6 +313,10 @@ static void xilinx_ethlite_realize(DeviceState *dev, E= rror **errp) sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mdio)= , 0)); =20 for (unsigned i =3D 0; i < 2; i++) { + memory_region_init_ram(&s->port[i].txbuf, OBJECT(dev), + i ? "ethlite.tx[1]buf" : "ethlite.tx[0]buf", + BUFSZ_MAX, &error_abort); + memory_region_add_subregion(&s->mmio, 0x0800 * i, &s->port[i].txbu= f); memory_region_init_io(&s->port[i].txio, OBJECT(dev), ð_porttx_ops, s, i ? "ethlite.tx[1]io" : "ethlite.tx[0]io", @@ -373,6 +324,11 @@ static void xilinx_ethlite_realize(DeviceState *dev, E= rror **errp) memory_region_add_subregion(&s->mmio, i ? A_TX_BASE1 : A_TX_BASE0, &s->port[i].txio); =20 + memory_region_init_ram(&s->port[i].rxbuf, OBJECT(dev), + i ? "ethlite.rx[1]buf" : "ethlite.rx[0]buf", + BUFSZ_MAX, &error_abort); + memory_region_add_subregion(&s->mmio, 0x1000 + 0x0800 * i, + &s->port[i].rxbuf); memory_region_init_io(&s->port[i].rxio, OBJECT(dev), ð_portrx_ops, s, i ? "ethlite.rx[1]io" : "ethlite.rx[0]io", @@ -393,9 +349,6 @@ static void xilinx_ethlite_init(Object *obj) XlnxXpsEthLite *s =3D XILINX_ETHLITE(obj); =20 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); - - memory_region_init_io(&s->mmio, obj, ð_ops, s, - "xlnx.xps-ethernetlite", R_MAX * 4); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); } =20 --=20 2.45.2