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Iglesias" , qemu-arm@nongnu.org, Richard Henderson , Thomas Huth , Anton Johansson , Bernhard Beschow , Alistair Francis , Paolo Bonzini , Gustavo Romero , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Peter Maydell , Jason Wang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Edgar E . Iglesias" Subject: [PATCH RESEND v2 13/19] hw/net/xilinx_ethlite: Map RX_CTRL as MMIO Date: Thu, 14 Nov 2024 22:00:04 +0100 Message-ID: <20241114210010.34502-14-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114210010.34502-1-philmd@linaro.org> References: <20241114210010.34502-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731618199582116600 Declare RX registers as MMIO region, split it out of the current mixed RAM/MMIO region. The memory flat view becomes: (qemu) info mtree -f FlatView #0 Root memory region: system 0000000081000000-00000000810007e3 (prio 0, i/o): xlnx.xps-ethernetlite 00000000810007e4-00000000810007f3 (prio 0, i/o): ethlite.mdio 00000000810007f4-00000000810017fb (prio 0, i/o): xlnx.xps-ethernetlite = @00000000000007f4 00000000810017fc-00000000810017ff (prio 0, i/o): ethlite.rx[0]io 0000000081001800-0000000081001ffb (prio 0, i/o): xlnx.xps-ethernetlite = @0000000000001800 0000000081001ffc-0000000081001fff (prio 0, i/o): ethlite.rx[1]io Reviewed-by: Edgar E. Iglesias Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/net/xilinx_ethlite.c | 82 +++++++++++++++++++++++++++++++++-------- 1 file changed, 67 insertions(+), 15 deletions(-) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 674f805d76..d8f5a06182 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -49,11 +49,16 @@ #define R_TX_CTRL1 (0x0ffc / 4) =20 #define R_RX_BUF0 (0x1000 / 4) -#define R_RX_CTRL0 (0x17fc / 4) +#define A_RX_BASE0 0x17fc #define R_RX_BUF1 (0x1800 / 4) -#define R_RX_CTRL1 (0x1ffc / 4) +#define A_RX_BASE1 0x1ffc #define R_MAX (0x2000 / 4) =20 +enum { + RX_CTRL =3D 0, + RX_MAX +}; + #define GIE_GIE 0x80000000 =20 #define CTRL_I 0x8 @@ -62,6 +67,8 @@ =20 typedef struct XlnxXpsEthLitePort { + MemoryRegion rxio; + struct { uint32_t tx_len; uint32_t tx_gie; @@ -119,6 +126,55 @@ static void *rxbuf_ptr(XlnxXpsEthLite *s, unsigned por= t_index) return &s->regs[rxbase + R_RX_BUF0]; } =20 +static uint64_t port_rx_read(void *opaque, hwaddr addr, unsigned int size) +{ + XlnxXpsEthLite *s =3D opaque; + unsigned port_index =3D addr_to_port_index(addr); + uint32_t r =3D 0; + + switch (addr >> 2) { + case RX_CTRL: + r =3D s->port[port_index].reg.rx_ctrl; + break; + default: + g_assert_not_reached(); + } + + return r; +} + +static void port_rx_write(void *opaque, hwaddr addr, uint64_t value, + unsigned int size) +{ + XlnxXpsEthLite *s =3D opaque; + unsigned port_index =3D addr_to_port_index(addr); + + switch (addr >> 2) { + case RX_CTRL: + if (!(value & CTRL_S)) { + qemu_flush_queued_packets(qemu_get_queue(s->nic)); + } + s->port[port_index].reg.rx_ctrl =3D value; + break; + default: + g_assert_not_reached(); + } +} + +static const MemoryRegionOps eth_portrx_ops =3D { + .read =3D port_rx_read, + .write =3D port_rx_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + static uint64_t eth_read(void *opaque, hwaddr addr, unsigned int size) { @@ -144,11 +200,6 @@ eth_read(void *opaque, hwaddr addr, unsigned int size) r =3D s->port[port_index].reg.tx_ctrl; break; =20 - case R_RX_CTRL1: - case R_RX_CTRL0: - r =3D s->port[port_index].reg.rx_ctrl; - break; - default: r =3D tswap32(s->regs[addr]); break; @@ -189,14 +240,6 @@ eth_write(void *opaque, hwaddr addr, break; =20 /* Keep these native. */ - case R_RX_CTRL0: - case R_RX_CTRL1: - if (!(value & CTRL_S)) { - qemu_flush_queued_packets(qemu_get_queue(s->nic)); - } - s->port[port_index].reg.rx_ctrl =3D value; - break; - case R_TX_LEN0: case R_TX_LEN1: s->port[port_index].reg.tx_len =3D value; @@ -289,6 +332,15 @@ static void xilinx_ethlite_realize(DeviceState *dev, E= rror **errp) memory_region_add_subregion(&s->mmio, A_MDIO_BASE, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mdio)= , 0)); =20 + for (unsigned i =3D 0; i < 2; i++) { + memory_region_init_io(&s->port[i].rxio, OBJECT(dev), + ð_portrx_ops, s, + i ? "ethlite.rx[1]io" : "ethlite.rx[0]io", + 4 * RX_MAX); + memory_region_add_subregion(&s->mmio, i ? A_RX_BASE1 : A_RX_BASE0, + &s->port[i].rxio); + } + qemu_macaddr_default_if_unset(&s->conf.macaddr); s->nic =3D qemu_new_nic(&net_xilinx_ethlite_info, &s->conf, object_get_typename(OBJECT(dev)), dev->id, --=20 2.45.2