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([71.212.136.242]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ea024ec723sm1484438a91.46.2024.11.14.08.01.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:01:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731600097; x=1732204897; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=oFR54WJ7Z7wCqfLri0LCaQ3ITtfM85rp0V8bo+nOxWA=; b=QN+Tt6rYXifuXSBZjImQwSCH4hazW2pmsUppYijDkooQppGCwF8Zeom+Tt87NCCknA PKTIb2SuDSnKU/TUZygzryUM7Ed037XquoyspZ1lyxr8cbg7RK+joHBQlvmiMIzRd7Wc KWAoemzFolfSxMiXqLkn+qaWF/4UsoNCzbP2Rtr12EbjzOP0sn/EdcoC8Oao/EL13nft Reu91QNLXdkfYjWsDwek1zh4hFvjKuVt5U48psoljF1LljP7tZAPY9kd35Uh9I8EQ2ZY XCDocsGMQfXnFKPSr9aDHxYI2hjnh9nn72NJSV6LPtKXGyAIJExg5gqe7+uhKNYG90iC nBqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731600097; x=1732204897; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oFR54WJ7Z7wCqfLri0LCaQ3ITtfM85rp0V8bo+nOxWA=; b=RrXr5pGpoDs/ykzhJGayu12xCeJ0eFgk89jnKVqrZOz8UOwVvw9AuHFxdlNQT5A9nB 2BmAA/3fDXFKhvuUK6OjA0kE/TT8jIMfAUvU3j8UbXxSYFtmiX1ypaujfOVrUQxqmX12 GkzGjWC2Fdo4qLT4FW7wutxst/IKrXS6PYTGbiqH66Qu7YBszFaI53/YyssgIv61swGJ ES34XsL/SJaCBj31Gp99IbYaVzeeBgf1Oo9RjrkoyOXQ4d/RQt81+Y5t0ryLGGFETWn4 W7Rydsx/eBDViJ/TZKUT+9QvcjZYlAs1MROuuGF2xSfIc3lH/KPiL9R/LV5usazAMyAu nNRw== X-Gm-Message-State: AOJu0YzTcNvOZjuEczxq+oRsRBtV+1vyqE9ymmQUqFlU0PinsKNpCxiM YGH+QJmRqYExx4Us/UP8oTwkQIL121izuzBhuZOWiLN2KjsMWm7m4xAaQHDnPduiSo71+nO/x0a r X-Google-Smtp-Source: AGHT+IEtgfnvE8wucOMCwWAfgCmZ8rB63917GWQJPZgDBTKLsxHXYSjWkH9si5U7nV6EibzRKcXRgA== X-Received: by 2002:a17:90b:3948:b0:2e2:d181:6808 with SMTP id 98e67ed59e1d1-2e9f2d5da6fmr8756010a91.30.1731600097110; Thu, 14 Nov 2024 08:01:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 06/54] accel/tcg: Assert non-zero length in tlb_flush_range_by_mmuidx* Date: Thu, 14 Nov 2024 08:00:42 -0800 Message-ID: <20241114160131.48616-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241114160131.48616-1-richard.henderson@linaro.org> References: <20241114160131.48616-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731600148381116600 Content-Type: text/plain; charset="utf-8" Next patches will assume non-zero length. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/cputlb.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 77b972fd93..1346a26d90 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -791,6 +791,7 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr add= r, TLBFlushRangeData d; =20 assert_cpu_is_self(cpu); + assert(len !=3D 0); =20 /* * If all bits are significant, and len is small, @@ -830,6 +831,8 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState= *src_cpu, TLBFlushRangeData d, *p; CPUState *dst_cpu; =20 + assert(len !=3D 0); + /* * If all bits are significant, and len is small, * this devolves to tlb_flush_page. --=20 2.43.0