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([71.212.136.242]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7246a9bab70sm1417926b3a.152.2024.11.14.08.05.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:05:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731600318; x=1732205118; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=hjYrYa5EsHh3SE2oZ1zQ8eTrBOhtgNkNlLaG4FiIf5M=; b=iXIqKF3UcTJ2ELfpuHHTsvloBCJ/VdGkHM58d54rtNF0yPlMwgHAwUOou+jBxyVqhJ SQX290WHeKHa1+mCnt6GTvEPiXn/4ycs+mNWr1dDAU3s+Jvc6EfuYMsh8c84kP+nvYHK lHgQcnJGh8ugv61XTgdFGnatANCQsNCEorJmob3qckucanMJGmBVBOMdmRxRLO87nLui FudC8LOsE5xymPywi2v/Iz+20vrm9E1j2aSGyiU7KcJnTEeh0tAnbkmgiuz9Ts8PAj7D Mp7iXPtxr7I1POxIE0cXRMy3mb7/S5ju5gfukUzhS2jpB903d31vMNXtTOCAIDl+KZ28 bA9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731600318; x=1732205118; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hjYrYa5EsHh3SE2oZ1zQ8eTrBOhtgNkNlLaG4FiIf5M=; b=t6HDKuMUeeNjqfjwaRQgoLpIAoN75CJzcWQWE0hcUJj6/XjaBeg5V6Rg47J8FKuC4M A/qGrh627c166P7IdEjscVU3nAb3DcoitDvxehs+5Om1zniy/SeXPk6W7MCyAP93up+t kzxBSE23Zt4hscPsO2tdjhj+YJ75qOAw96QiJXUCeHg14zDOiVLH3mXimmUErCOxtenZ 7mC8MzyZEYgeorGAKeyRUBAZHpItddYYbC8n3mQVe5hmbVidyo4TrGU08VSfbiO/m0sO qni+73XpCXvg+3HwNY+SYbEn0RdAL30bqoTq/Wpg8tIdIittRo0Xk+poRMx9RVygV5rj iCaw== X-Gm-Message-State: AOJu0YzpVafqnm88nUftXCidAXtYZkFJ7ufmvBVMh47cg0RZ54XALamf Ik3j8rBkGvXBRM30hC/ZJGPeLfLjn6lCd6bFogMVZXS/kckYWoZqgwZwsIacJN+jGQHGaZq88vZ f X-Google-Smtp-Source: AGHT+IGfHX5pYHxsHA7K4uM46iOMwPpNfvOwCwQV10VKTCN6yRoVDj0v4MXJ81BIqIbxRSbsPDjEqA== X-Received: by 2002:a05:6a00:234b:b0:71e:7d52:fa8c with SMTP id d2e1a72fcca58-72457a7563bmr9083242b3a.22.1731600318394; Thu, 14 Nov 2024 08:05:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 51/54] accel/tcg: Drop TCGCPUOps.tlb_fill Date: Thu, 14 Nov 2024 08:01:27 -0800 Message-ID: <20241114160131.48616-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241114160131.48616-1-richard.henderson@linaro.org> References: <20241114160131.48616-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731600701200116600 Content-Type: text/plain; charset="utf-8" Now that all targets have been converted to tlb_fill_align, remove the tlb_fill hook. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- include/hw/core/tcg-cpu-ops.h | 10 ---------- accel/tcg/cputlb.c | 19 ++++--------------- 2 files changed, 4 insertions(+), 25 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 663efb9133..70cafcc6cd 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -157,16 +157,6 @@ struct TCGCPUOps { bool (*tlb_fill_align)(CPUState *cpu, CPUTLBEntryFull *out, vaddr addr, MMUAccessType access_type, int mmu_idx, MemOp memop, int size, bool probe, uintptr_t ra= ); - /** - * @tlb_fill: Handle a softmmu tlb miss - * - * If the access is valid, call tlb_set_page and return true; - * if the access is invalid and probe is true, return false; - * otherwise raise an exception and do not return. - */ - bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); /** * @do_transaction_failed: Callback for handling failed memory transac= tions * (ie bus faults or external aborts; not MMU faults) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 7f63dc3fd8..ec597ed6f5 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1222,23 +1222,12 @@ static bool tlb_fill_align(CPUState *cpu, vaddr add= r, MMUAccessType type, int mmu_idx, MemOp memop, int size, bool probe, uintptr_t ra) { - const TCGCPUOps *ops =3D cpu->cc->tcg_ops; CPUTLBEntryFull full; =20 - if (ops->tlb_fill_align) { - if (ops->tlb_fill_align(cpu, &full, addr, type, mmu_idx, - memop, size, probe, ra)) { - tlb_set_page_full(cpu, mmu_idx, addr, &full); - return true; - } - } else { - /* Legacy behaviour is alignment before paging. */ - if (addr & ((1u << memop_alignment_bits(memop)) - 1)) { - ops->do_unaligned_access(cpu, addr, type, mmu_idx, ra); - } - if (ops->tlb_fill(cpu, addr, size, type, mmu_idx, probe, ra)) { - return true; - } + if (cpu->cc->tcg_ops->tlb_fill_align(cpu, &full, addr, type, mmu_idx, + memop, size, probe, ra)) { + tlb_set_page_full(cpu, mmu_idx, addr, &full); + return true; } assert(probe); return false; --=20 2.43.0