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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731600874134116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/tricore/cpu.h | 7 ++++--- target/tricore/cpu.c | 2 +- target/tricore/helper.c | 19 ++++++++++++------- 3 files changed, 17 insertions(+), 11 deletions(-) diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 220af69fc2..5f141ce8f3 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -268,8 +268,9 @@ static inline void cpu_get_tb_cpu_state(CPUTriCoreState= *env, vaddr *pc, #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU =20 /* helpers.c */ -bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); +bool tricore_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, + vaddr addr, MMUAccessType access_type, + int mmu_idx, MemOp memop, int size, + bool probe, uintptr_t retaddr); =20 #endif /* TRICORE_CPU_H */ diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 1a26171590..29e0b5d129 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -173,7 +173,7 @@ static const TCGCPUOps tricore_tcg_ops =3D { .initialize =3D tricore_tcg_init, .synchronize_from_tb =3D tricore_cpu_synchronize_from_tb, .restore_state_to_opc =3D tricore_restore_state_to_opc, - .tlb_fill =3D tricore_cpu_tlb_fill, + .tlb_fill_align =3D tricore_cpu_tlb_fill_align, .cpu_exec_interrupt =3D tricore_cpu_exec_interrupt, .cpu_exec_halt =3D tricore_cpu_has_work, }; diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 7014255f77..8c6bf63298 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -64,16 +64,19 @@ static void raise_mmu_exception(CPUTriCoreState *env, t= arget_ulong address, { } =20 -bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType rw, int mmu_idx, - bool probe, uintptr_t retaddr) +bool tricore_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, + vaddr address, MMUAccessType access_type, + int mmu_idx, MemOp memop, int size, + bool probe, uintptr_t retaddr) { CPUTriCoreState *env =3D cpu_env(cs); hwaddr physical; int prot; int ret =3D 0; + int rw =3D access_type & 1; + + /* TODO: alignment faults not currently handled. */ =20 - rw &=3D 1; ret =3D get_physical_address(env, &physical, &prot, address, rw, mmu_idx); =20 @@ -82,9 +85,11 @@ bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, __func__, address, ret, physical, prot); =20 if (ret =3D=3D TLBRET_MATCH) { - tlb_set_page(cs, address & TARGET_PAGE_MASK, - physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, - mmu_idx, TARGET_PAGE_SIZE); + memset(out, 0, sizeof(*out)); + out->phys_addr =3D physical; + out->prot =3D prot | PAGE_EXEC; + out->lg_page_size =3D TARGET_PAGE_BITS; + out->attrs =3D MEMTXATTRS_UNSPECIFIED; return true; } else { assert(ret < 0); --=20 2.43.0