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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731600779464116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/sparc/cpu.h | 8 ++++--- target/sparc/cpu.c | 2 +- target/sparc/mmu_helper.c | 44 +++++++++++++++++++++++++-------------- 3 files changed, 34 insertions(+), 20 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index f517e5a383..4c8927e9fa 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -4,6 +4,7 @@ #include "qemu/bswap.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "exec/memop.h" #include "qemu/cpu-float.h" =20 #if !defined(TARGET_SPARC64) @@ -596,9 +597,10 @@ G_NORETURN void cpu_raise_exception_ra(CPUSPARCState *= , int, uintptr_t); void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); void sparc_cpu_list(void); /* mmu_helper.c */ -bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); +bool sparc_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, + vaddr addr, MMUAccessType access_type, + int mmu_idx, MemOp memop, int size, + bool probe, uintptr_t retaddr); target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmule= v); void dump_mmu(CPUSPARCState *env); =20 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index dd7af86de7..57ae53bd71 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -932,7 +932,7 @@ static const TCGCPUOps sparc_tcg_ops =3D { .restore_state_to_opc =3D sparc_restore_state_to_opc, =20 #ifndef CONFIG_USER_ONLY - .tlb_fill =3D sparc_cpu_tlb_fill, + .tlb_fill_align =3D sparc_cpu_tlb_fill_align, .cpu_exec_interrupt =3D sparc_cpu_exec_interrupt, .cpu_exec_halt =3D sparc_cpu_has_work, .do_interrupt =3D sparc_cpu_do_interrupt, diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 9ff06026b8..32766a37d6 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -203,12 +203,12 @@ static int get_physical_address(CPUSPARCState *env, C= PUTLBEntryFull *full, } =20 /* Perform address translation */ -bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +bool sparc_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, + vaddr address, MMUAccessType access_type, + int mmu_idx, MemOp memop, int size, + bool probe, uintptr_t retaddr) { CPUSPARCState *env =3D cpu_env(cs); - CPUTLBEntryFull full =3D {}; target_ulong vaddr; int error_code =3D 0, access_index; =20 @@ -220,16 +220,21 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, */ assert(!probe); =20 + if (address & ((1 << memop_alignment_bits(memop)) - 1)) { + sparc_cpu_do_unaligned_access(cs, address, access_type, + mmu_idx, retaddr); + } + + memset(out, 0, sizeof(*out)); address &=3D TARGET_PAGE_MASK; - error_code =3D get_physical_address(env, &full, &access_index, + error_code =3D get_physical_address(env, out, &access_index, address, access_type, mmu_idx); vaddr =3D address; if (likely(error_code =3D=3D 0)) { qemu_log_mask(CPU_LOG_MMU, "Translate at %" VADDR_PRIx " -> " HWADDR_FMT_plx ", vaddr " TARGET_FMT_lx "\n", - address, full.phys_addr, vaddr); - tlb_set_page_full(cs, mmu_idx, vaddr, &full); + address, out->phys_addr, vaddr); return true; } =20 @@ -244,8 +249,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, permissions. If no mapping is available, redirect accesses to neverland. Fake/overridden mappings will be flushed when switching to normal mode. */ - full.prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - tlb_set_page_full(cs, mmu_idx, vaddr, &full); + out->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; return true; } else { if (access_type =3D=3D MMU_INST_FETCH) { @@ -754,22 +758,30 @@ static int get_physical_address(CPUSPARCState *env, C= PUTLBEntryFull *full, } =20 /* Perform address translation */ -bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +bool sparc_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, + vaddr address, MMUAccessType access_type, + int mmu_idx, MemOp memop, int size, + bool probe, uintptr_t retaddr) { CPUSPARCState *env =3D cpu_env(cs); - CPUTLBEntryFull full =3D {}; int error_code =3D 0, access_index; =20 + if (address & ((1 << memop_alignment_bits(memop)) - 1)) { + if (probe) { + return false; + } + sparc_cpu_do_unaligned_access(cs, address, access_type, + mmu_idx, retaddr); + } + + memset(out, 0, sizeof(*out)); address &=3D TARGET_PAGE_MASK; - error_code =3D get_physical_address(env, &full, &access_index, + error_code =3D get_physical_address(env, out, &access_index, address, access_type, mmu_idx); if (likely(error_code =3D=3D 0)) { - trace_mmu_helper_mmu_fault(address, full.phys_addr, mmu_idx, env->= tl, + trace_mmu_helper_mmu_fault(address, out->phys_addr, mmu_idx, env->= tl, env->dmmu.mmu_primary_context, env->dmmu.mmu_secondary_context); - tlb_set_page_full(cs, mmu_idx, address, &full); return true; } if (probe) { --=20 2.43.0