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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731600654974116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/sh4/cpu.h | 8 +++++--- target/sh4/cpu.c | 2 +- target/sh4/helper.c | 24 +++++++++++++++++------- 3 files changed, 23 insertions(+), 11 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index d928bcf006..161efdefcf 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -22,6 +22,7 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "exec/memop.h" #include "qemu/cpu-float.h" =20 /* CPU Subtypes */ @@ -251,9 +252,10 @@ void sh4_translate_init(void); =20 #if !defined(CONFIG_USER_ONLY) hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); +bool superh_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, + vaddr addr, MMUAccessType access_type, + int mmu_idx, MemOp memop, int size, + bool probe, uintptr_t retaddr); void superh_cpu_do_interrupt(CPUState *cpu); bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); void cpu_sh4_invalidate_tlb(CPUSH4State *s); diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 8f07261dcf..8ca8b90e3c 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -252,7 +252,7 @@ static const TCGCPUOps superh_tcg_ops =3D { .restore_state_to_opc =3D superh_restore_state_to_opc, =20 #ifndef CONFIG_USER_ONLY - .tlb_fill =3D superh_cpu_tlb_fill, + .tlb_fill_align =3D superh_cpu_tlb_fill_align, .cpu_exec_interrupt =3D superh_cpu_exec_interrupt, .cpu_exec_halt =3D superh_cpu_has_work, .do_interrupt =3D superh_cpu_do_interrupt, diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 9659c69550..543ac1b843 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -792,22 +792,32 @@ bool superh_cpu_exec_interrupt(CPUState *cs, int inte= rrupt_request) return false; } =20 -bool superh_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +bool superh_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, + vaddr address, MMUAccessType access_type, + int mmu_idx, MemOp memop, int size, + bool probe, uintptr_t retaddr) { CPUSH4State *env =3D cpu_env(cs); int ret; - target_ulong physical; int prot; =20 + if (address & ((1 << memop_alignment_bits(memop)) - 1)) { + if (probe) { + return false; + } + superh_cpu_do_unaligned_access(cs, address, access_type, + mmu_idx, retaddr); + } + ret =3D get_physical_address(env, &physical, &prot, address, access_ty= pe); =20 if (ret =3D=3D MMU_OK) { - address &=3D TARGET_PAGE_MASK; - physical &=3D TARGET_PAGE_MASK; - tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZ= E); + memset(out, 0, sizeof(*out)); + out->phys_addr =3D physical; + out->prot =3D prot; + out->lg_page_size =3D TARGET_PAGE_BITS; + out->attrs =3D MEMTXATTRS_UNSPECIFIED; return true; } if (probe) { --=20 2.43.0