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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731600631083116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/rx/cpu.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 65a74ce720..c83a582141 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -161,16 +161,19 @@ static void rx_cpu_disas_set_info(CPUState *cpu, disa= ssemble_info *info) info->print_insn =3D print_insn_rx; } =20 -static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +static bool rx_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, + vaddr addr, MMUAccessType access_type, + int mmu_idx, MemOp memop, int size, + bool probe, uintptr_t retaddr) { - uint32_t address, physical, prot; + /* TODO: alignment faults not currently handled. */ =20 /* Linear mapping */ - address =3D physical =3D addr & TARGET_PAGE_MASK; - prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); + memset(out, 0, sizeof(*out)); + out->phys_addr =3D addr; + out->prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + out->lg_page_size =3D TARGET_PAGE_BITS; + out->attrs =3D MEMTXATTRS_UNSPECIFIED; return true; } =20 @@ -195,7 +198,7 @@ static const TCGCPUOps rx_tcg_ops =3D { .initialize =3D rx_translate_init, .synchronize_from_tb =3D rx_cpu_synchronize_from_tb, .restore_state_to_opc =3D rx_restore_state_to_opc, - .tlb_fill =3D rx_cpu_tlb_fill, + .tlb_fill_align =3D rx_cpu_tlb_fill_align, =20 #ifndef CONFIG_USER_ONLY .cpu_exec_interrupt =3D rx_cpu_exec_interrupt, --=20 2.43.0