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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731600799731116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/ppc/internal.h | 7 ++++--- target/ppc/cpu_init.c | 2 +- target/ppc/mmu_helper.c | 21 ++++++++++++++++----- 3 files changed, 21 insertions(+), 9 deletions(-) diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 20fb2ec593..9d132d35a1 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -273,9 +273,10 @@ void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr, MMUAccessType access_type, bool maperr, uintptr_t ra); #else -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); +bool ppc_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, + vaddr addr, MMUAccessType access_type, + int mmu_idx, MemOp memop, int size, + bool probe, uintptr_t ra); G_NORETURN void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int= mmu_idx, uintptr_t retaddr); diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index efcb80d1c2..387c7ff2da 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7422,7 +7422,7 @@ static const TCGCPUOps ppc_tcg_ops =3D { #ifdef CONFIG_USER_ONLY .record_sigsegv =3D ppc_cpu_record_sigsegv, #else - .tlb_fill =3D ppc_cpu_tlb_fill, + .tlb_fill_align =3D ppc_cpu_tlb_fill_align, .cpu_exec_interrupt =3D ppc_cpu_exec_interrupt, .cpu_exec_halt =3D ppc_cpu_has_work, .do_interrupt =3D ppc_cpu_do_interrupt, diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index b167b37e0a..bf98e0efb0 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -1357,18 +1357,29 @@ void helper_check_tlb_flush_global(CPUPPCState *env) } =20 =20 -bool ppc_cpu_tlb_fill(CPUState *cs, vaddr eaddr, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +bool ppc_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, + vaddr eaddr, MMUAccessType access_type, + int mmu_idx, MemOp memop, int size, + bool probe, uintptr_t retaddr) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); hwaddr raddr; int page_size, prot; =20 + if (eaddr & ((1 << memop_alignment_bits(memop)) - 1)) { + if (probe) { + return false; + } + ppc_cpu_do_unaligned_access(cs, eaddr, access_type, mmu_idx, retad= dr); + } + if (ppc_xlate(cpu, eaddr, access_type, &raddr, &page_size, &prot, mmu_idx, !probe)) { - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MAS= K, - prot, mmu_idx, 1UL << page_size); + memset(out, 0, sizeof(*out)); + out->phys_addr =3D raddr; + out->prot =3D prot; + out->lg_page_size =3D page_size; + out->attrs =3D MEMTXATTRS_UNSPECIFIED; return true; } if (probe) { --=20 2.43.0