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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731600490196116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/openrisc/cpu.h | 8 +++++--- target/openrisc/cpu.c | 2 +- target/openrisc/mmu.c | 39 +++++++++++++++++++++------------------ 3 files changed, 27 insertions(+), 22 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index c9fe9ae12d..e177ad8b84 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -22,6 +22,7 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "exec/memop.h" #include "fpu/softfloat-types.h" =20 /** @@ -306,9 +307,10 @@ int print_insn_or1k(bfd_vma addr, disassemble_info *in= fo); #ifndef CONFIG_USER_ONLY hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 -bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); +bool openrisc_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, + vaddr addr, MMUAccessType access_type, + int mmu_idx, MemOp memop, int size, + bool probe, uintptr_t ra); =20 extern const VMStateDescription vmstate_openrisc_cpu; =20 diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index b96561d1f2..6aa04ff7d3 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -237,7 +237,7 @@ static const TCGCPUOps openrisc_tcg_ops =3D { .restore_state_to_opc =3D openrisc_restore_state_to_opc, =20 #ifndef CONFIG_USER_ONLY - .tlb_fill =3D openrisc_cpu_tlb_fill, + .tlb_fill_align =3D openrisc_cpu_tlb_fill_align, .cpu_exec_interrupt =3D openrisc_cpu_exec_interrupt, .cpu_exec_halt =3D openrisc_cpu_has_work, .do_interrupt =3D openrisc_cpu_do_interrupt, diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index c632d5230b..eafab356a6 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -104,39 +104,42 @@ static void raise_mmu_exception(OpenRISCCPU *cpu, tar= get_ulong address, cpu->env.lock_addr =3D -1; } =20 -bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +bool openrisc_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, + vaddr addr, MMUAccessType access_type, + int mmu_idx, MemOp memop, int size, + bool probe, uintptr_t retaddr) { OpenRISCCPU *cpu =3D OPENRISC_CPU(cs); - int excp =3D EXCP_DPF; int prot; hwaddr phys_addr; =20 + /* TODO: alignment faults not currently handled. */ + if (mmu_idx =3D=3D MMU_NOMMU_IDX) { /* The mmu is disabled; lookups never fail. */ get_phys_nommu(&phys_addr, &prot, addr); - excp =3D 0; } else { bool super =3D mmu_idx =3D=3D MMU_SUPERVISOR_IDX; int need =3D (access_type =3D=3D MMU_INST_FETCH ? PAGE_EXEC : access_type =3D=3D MMU_DATA_STORE ? PAGE_WRITE : PAGE_READ); - excp =3D get_phys_mmu(cpu, &phys_addr, &prot, addr, need, super); + int excp =3D get_phys_mmu(cpu, &phys_addr, &prot, addr, need, supe= r); + + if (unlikely(excp)) { + if (probe) { + return false; + } + raise_mmu_exception(cpu, addr, excp); + cpu_loop_exit_restore(cs, retaddr); + } } =20 - if (likely(excp =3D=3D 0)) { - tlb_set_page(cs, addr & TARGET_PAGE_MASK, - phys_addr & TARGET_PAGE_MASK, prot, - mmu_idx, TARGET_PAGE_SIZE); - return true; - } - if (probe) { - return false; - } - - raise_mmu_exception(cpu, addr, excp); - cpu_loop_exit_restore(cs, retaddr); + memset(out, 0, sizeof(*out)); + out->phys_addr =3D phys_addr; + out->prot =3D prot; + out->lg_page_size =3D TARGET_PAGE_BITS; + out->attrs =3D MEMTXATTRS_UNSPECIFIED; + return true; } =20 hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) --=20 2.43.0