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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731600725344116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/mips/tcg/tcg-internal.h | 6 +++--- target/mips/cpu.c | 2 +- target/mips/tcg/sysemu/tlb_helper.c | 29 ++++++++++++++++++++--------- 3 files changed, 24 insertions(+), 13 deletions(-) diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index aef032c48d..f4b00354af 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -61,9 +61,9 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr = physaddr, MemTxResult response, uintptr_t retadd= r); void cpu_mips_tlb_flush(CPUMIPSState *env); =20 -bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); +bool mips_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr add= ress, + MMUAccessType access_type, int mmu_idx, + MemOp memop, int size, bool probe, uintptr_t = ra); =20 void mips_semihosting(CPUMIPSState *env); =20 diff --git a/target/mips/cpu.c b/target/mips/cpu.c index d0a43b6d5c..3a453c9285 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -556,7 +556,7 @@ static const TCGCPUOps mips_tcg_ops =3D { .restore_state_to_opc =3D mips_restore_state_to_opc, =20 #if !defined(CONFIG_USER_ONLY) - .tlb_fill =3D mips_cpu_tlb_fill, + .tlb_fill_align =3D mips_cpu_tlb_fill_align, .cpu_exec_interrupt =3D mips_cpu_exec_interrupt, .cpu_exec_halt =3D mips_cpu_has_work, .do_interrupt =3D mips_cpu_do_interrupt, diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/t= lb_helper.c index e98bb95951..ac76396525 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -904,15 +904,28 @@ refill: } #endif =20 -bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +bool mips_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr add= ress, + MMUAccessType access_type, int mmu_idx, + MemOp memop, int size, + bool probe, uintptr_t retaddr) { CPUMIPSState *env =3D cpu_env(cs); hwaddr physical; int prot; int ret =3D TLBRET_BADADDR; =20 + if (address & ((1 << memop_alignment_bits(memop)) - 1)) { + if (probe) { + return false; + } + mips_cpu_do_unaligned_access(cs, address, access_type, + mmu_idx, retaddr); + } + + memset(out, 0, sizeof(*out)); + out->attrs =3D MEMTXATTRS_UNSPECIFIED; + out->lg_page_size =3D TARGET_PAGE_BITS; + /* data access */ /* XXX: put correct access by using cpu_restore_state() correctly */ ret =3D get_physical_address(env, &physical, &prot, address, @@ -930,9 +943,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, break; } if (ret =3D=3D TLBRET_MATCH) { - tlb_set_page(cs, address & TARGET_PAGE_MASK, - physical & TARGET_PAGE_MASK, prot, - mmu_idx, TARGET_PAGE_SIZE); + out->phys_addr =3D physical; + out->prot =3D prot; return true; } #if !defined(TARGET_MIPS64) @@ -948,9 +960,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, ret =3D get_physical_address(env, &physical, &prot, address, access_type, mmu_idx); if (ret =3D=3D TLBRET_MATCH) { - tlb_set_page(cs, address & TARGET_PAGE_MASK, - physical & TARGET_PAGE_MASK, prot, - mmu_idx, TARGET_PAGE_SIZE); + out->phys_addr =3D physical; + out->prot =3D prot; return true; } } --=20 2.43.0