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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731600735368116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/microblaze/cpu.h | 7 +++---- target/microblaze/cpu.c | 2 +- target/microblaze/helper.c | 33 ++++++++++++++++++++------------- 3 files changed, 24 insertions(+), 18 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 3e5a3e5c60..b0eadfd9b1 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -421,10 +421,9 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *en= v, vaddr *pc, } =20 #if !defined(CONFIG_USER_ONLY) -bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); - +bool mb_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addre= ss, + MMUAccessType access_type, int mmu_idx, + MemOp memop, int size, bool probe, uintptr_t ra= ); void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 710eb1146c..212cad2143 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -425,7 +425,7 @@ static const TCGCPUOps mb_tcg_ops =3D { .restore_state_to_opc =3D mb_restore_state_to_opc, =20 #ifndef CONFIG_USER_ONLY - .tlb_fill =3D mb_cpu_tlb_fill, + .tlb_fill_align =3D mb_cpu_tlb_fill_align, .cpu_exec_interrupt =3D mb_cpu_exec_interrupt, .cpu_exec_halt =3D mb_cpu_has_work, .do_interrupt =3D mb_cpu_do_interrupt, diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 5d3259ce31..b6375564b4 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -36,37 +36,44 @@ static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu, } } =20 -bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +bool mb_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addre= ss, + MMUAccessType access_type, int mmu_idx, + MemOp memop, int size, + bool probe, uintptr_t retaddr) { MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); CPUMBState *env =3D &cpu->env; MicroBlazeMMULookup lu; unsigned int hit; - int prot; - MemTxAttrs attrs =3D {}; =20 - attrs.secure =3D mb_cpu_access_is_secure(cpu, access_type); + if (address & ((1 << memop_alignment_bits(memop)) - 1)) { + if (probe) { + return false; + } + mb_cpu_do_unaligned_access(cs, address, access_type, mmu_idx, reta= ddr); + } + + memset(out, 0, sizeof(*out)); + out->attrs.secure =3D mb_cpu_access_is_secure(cpu, access_type); + out->lg_page_size =3D TARGET_PAGE_BITS; =20 if (mmu_idx =3D=3D MMU_NOMMU_IDX) { /* MMU disabled or not available. */ - address &=3D TARGET_PAGE_MASK; - prot =3D PAGE_RWX; - tlb_set_page_with_attrs(cs, address, address, attrs, prot, mmu_idx, - TARGET_PAGE_SIZE); + out->phys_addr =3D address; + out->prot =3D PAGE_RWX; return true; } =20 hit =3D mmu_translate(cpu, &lu, address, access_type, mmu_idx); if (likely(hit)) { - uint32_t vaddr =3D address & TARGET_PAGE_MASK; + uint32_t vaddr =3D address; uint32_t paddr =3D lu.paddr + vaddr - lu.vaddr; =20 qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=3D%d v=3D%x p=3D%x prot=3D= %x\n", mmu_idx, vaddr, paddr, lu.prot); - tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, lu.prot, mmu_idx, - TARGET_PAGE_SIZE); + + out->phys_addr =3D paddr; + out->prot =3D lu.prot; return true; } =20 --=20 2.43.0