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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731600624937116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- target/avr/cpu.h | 7 ++++--- target/avr/cpu.c | 2 +- target/avr/helper.c | 19 ++++++++++++------- 3 files changed, 17 insertions(+), 11 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 4725535102..cdd3bcd418 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -23,6 +23,7 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "exec/memop.h" =20 #ifdef CONFIG_USER_ONLY #error "AVR 8-bit does not support user mode" @@ -238,9 +239,9 @@ static inline void cpu_set_sreg(CPUAVRState *env, uint8= _t sreg) env->sregI =3D (sreg >> 7) & 0x01; } =20 -bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); +bool avr_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr, + MMUAccessType access_type, int mmu_idx, + MemOp memop, int size, bool probe, uintptr_t r= a); =20 #include "exec/cpu-all.h" =20 diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 3132842d56..a7fe869396 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -211,7 +211,7 @@ static const TCGCPUOps avr_tcg_ops =3D { .restore_state_to_opc =3D avr_restore_state_to_opc, .cpu_exec_interrupt =3D avr_cpu_exec_interrupt, .cpu_exec_halt =3D avr_cpu_has_work, - .tlb_fill =3D avr_cpu_tlb_fill, + .tlb_fill_align =3D avr_cpu_tlb_fill_align, .do_interrupt =3D avr_cpu_do_interrupt, }; =20 diff --git a/target/avr/helper.c b/target/avr/helper.c index 345708a1b3..a18f11aa9f 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -104,11 +104,11 @@ hwaddr avr_cpu_get_phys_page_debug(CPUState *cs, vadd= r addr) return addr; /* I assume 1:1 address correspondence */ } =20 -bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) +bool avr_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr addr= ess, + MMUAccessType access_type, int mmu_idx, + MemOp memop, int size, bool probe, uintptr_t r= a) { - int prot, page_size =3D TARGET_PAGE_SIZE; + int prot, lg_page_size =3D TARGET_PAGE_BITS; uint32_t paddr; =20 address &=3D TARGET_PAGE_MASK; @@ -141,15 +141,20 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, * to force tlb_fill to be called for the next access. */ if (probe) { - page_size =3D 1; + lg_page_size =3D 0; } else { cpu_env(cs)->fullacc =3D 1; - cpu_loop_exit_restore(cs, retaddr); + cpu_loop_exit_restore(cs, ra); } } } =20 - tlb_set_page(cs, address, paddr, prot, mmu_idx, page_size); + memset(out, 0, sizeof(*out)); + out->phys_addr =3D paddr; + out->prot =3D prot; + out->attrs =3D MEMTXATTRS_UNSPECIFIED; + out->lg_page_size =3D lg_page_size; + return true; } =20 --=20 2.43.0