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([71.212.136.242]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ea024ec723sm1484438a91.46.2024.11.14.08.01.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:01:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731600114; x=1732204914; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=9Yssv0jEMu3znLJwX6X9mSGXOOpGLG/4PsoO3zzU/j8=; b=XgsI8Y7WRvgNkYvNbvQCseP/ZqUaN/ZNKMN+yGY+OsZ/MzUt+7bDRWnntY5ueT3fSl czls36G4ttsu70Tj5JjKxcqJrEvYlN5GMcYuo0nsRzM9Y01ng5K5byZRHN5cxYgWg3rq rONvu/YuteAC+Owmxbfq8MPrX/mpvLWFX1el/39quU+fRrW+p3EjM2C+5W42RwbdvUmk 8JcgwAi5OJ5pKZiVBuhMr3ZYnx7CrhyaIrCcIgU4W6MqzXHONDf29uJpqFqggJJNse5y gHo5y6DMlkdYNXT1s9ZZ2Fn4XvuyEDk1pujFKufhycvUuntZNiJZO1jR+h41fu6I3/91 GoCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731600114; x=1732204914; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9Yssv0jEMu3znLJwX6X9mSGXOOpGLG/4PsoO3zzU/j8=; b=co25rNHQr1XaxeRXWBYd45Um+dOR64O/KXwyo49KbNYzfKoh42/gkzLm57su9ZXcPL H2njF7lSTfPJf3muY1cENcXtHoR2816TaCLINlejVEqm5HlavEibgU0fGxRVjoAed85v 8+z4oB4rbODzhMvVty8FjUho2VpVTqhG7sdyUdzDIU8FB8oJXTJ+QPFWNVB2FRAyZjeE pn3HWwDB/teg7ITlRjLxqV3uPNxnwluhRmLx1i/OhWaCfWlpiPx8C3WoErIWupc6+2A2 2vBdNAmuuMS6NKONMjTc/biOHCv4tVntejktEf3z+xMOkBmRd3AxCzawN7P78Qi7XPlK kppA== X-Gm-Message-State: AOJu0YzpjUI/KqBc4okCBBNXIu0JABvOyUH1+5ZCVk97+ie7YAEWfEKi qNAW+SngYKGQy2uicIiMRvbgYmIVlX48qDSSOoPKvfRnYbhw0cmSxeH+c9rYhvJyDHzA1xouwE8 b X-Google-Smtp-Source: AGHT+IFLdAAVJWloFL406nCZNpvgcVG5gYnNaGTp0OhtyT1eS3AqjXuJsSo+9xeXXm45DxgMRFh9vQ== X-Received: by 2002:a17:90b:51c4:b0:2e2:ffb0:89f6 with SMTP id 98e67ed59e1d1-2e9f2c78416mr9734707a91.15.1731600113640; Thu, 14 Nov 2024 08:01:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 25/54] accel/tcg: Return CPUTLBEntryFull not pointer in probe_access_full_mmu Date: Thu, 14 Nov 2024 08:01:01 -0800 Message-ID: <20241114160131.48616-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241114160131.48616-1-richard.henderson@linaro.org> References: <20241114160131.48616-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731600259044116600 Content-Type: text/plain; charset="utf-8" Return a copy of the structure, not a pointer. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- include/exec/exec-all.h | 2 +- accel/tcg/cputlb.c | 13 ++++++++----- target/arm/ptw.c | 10 +++++----- target/i386/tcg/sysemu/excp_helper.c | 8 ++++---- 4 files changed, 18 insertions(+), 15 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 2e4c4cc4b4..df7d0b5ad0 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -393,7 +393,7 @@ int probe_access_full(CPUArchState *env, vaddr addr, in= t size, */ int probe_access_full_mmu(CPUArchState *env, vaddr addr, int size, MMUAccessType access_type, int mmu_idx, - void **phost, CPUTLBEntryFull **pfull); + void **phost, CPUTLBEntryFull *pfull); =20 #endif /* !CONFIG_USER_ONLY */ #endif /* CONFIG_TCG */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 585f4171cc..81135524eb 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1439,25 +1439,28 @@ int probe_access_full(CPUArchState *env, vaddr addr= , int size, =20 int probe_access_full_mmu(CPUArchState *env, vaddr addr, int size, MMUAccessType access_type, int mmu_idx, - void **phost, CPUTLBEntryFull **pfull) + void **phost, CPUTLBEntryFull *pfull) { void *discard_phost; - CPUTLBEntryFull *discard_tlb; + CPUTLBEntryFull *full; =20 /* privately handle users that don't need full results */ phost =3D phost ? phost : &discard_phost; - pfull =3D pfull ? pfull : &discard_tlb; =20 int flags =3D probe_access_internal(env_cpu(env), addr, size, access_t= ype, - mmu_idx, true, phost, pfull, 0, fals= e); + mmu_idx, true, phost, &full, 0, fals= e); =20 /* Handle clean RAM pages. */ if (unlikely(flags & TLB_NOTDIRTY)) { int dirtysize =3D size =3D=3D 0 ? 1 : size; - notdirty_write(env_cpu(env), addr, dirtysize, *pfull, 0); + notdirty_write(env_cpu(env), addr, dirtysize, full, 0); flags &=3D ~TLB_NOTDIRTY; } =20 + if (pfull) { + *pfull =3D *full; + } + return flags; } =20 diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 9849949508..3ae5f524de 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -592,7 +592,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Transl= ate *ptw, ptw->out_space =3D s2.f.attrs.space; } else { #ifdef CONFIG_TCG - CPUTLBEntryFull *full; + CPUTLBEntryFull full; int flags; =20 env->tlb_fi =3D fi; @@ -604,10 +604,10 @@ static bool S1_ptw_translate(CPUARMState *env, S1Tran= slate *ptw, if (unlikely(flags & TLB_INVALID_MASK)) { goto fail; } - ptw->out_phys =3D full->phys_addr | (addr & ~TARGET_PAGE_MASK); - ptw->out_rw =3D full->prot & PAGE_WRITE; - pte_attrs =3D full->extra.arm.pte_attrs; - ptw->out_space =3D full->attrs.space; + ptw->out_phys =3D full.phys_addr | (addr & ~TARGET_PAGE_MASK); + ptw->out_rw =3D full.prot & PAGE_WRITE; + pte_attrs =3D full.extra.arm.pte_attrs; + ptw->out_space =3D full.attrs.space; #else g_assert_not_reached(); #endif diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index 02d3486421..168ff8e5f3 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -436,7 +436,7 @@ do_check_protect_pse36: * addresses) using the address with the A20 bit set. */ if (in->ptw_idx =3D=3D MMU_NESTED_IDX) { - CPUTLBEntryFull *full; + CPUTLBEntryFull full; int flags, nested_page_size; =20 flags =3D probe_access_full_mmu(env, paddr, 0, access_type, @@ -451,7 +451,7 @@ do_check_protect_pse36: } =20 /* Merge stage1 & stage2 protection bits. */ - prot &=3D full->prot; + prot &=3D full.prot; =20 /* Re-verify resulting protection. */ if ((prot & (1 << access_type)) =3D=3D 0) { @@ -459,8 +459,8 @@ do_check_protect_pse36: } =20 /* Merge stage1 & stage2 addresses to final physical address. */ - nested_page_size =3D 1 << full->lg_page_size; - paddr =3D (full->phys_addr & ~(nested_page_size - 1)) + nested_page_size =3D 1 << full.lg_page_size; + paddr =3D (full.phys_addr & ~(nested_page_size - 1)) | (paddr & (nested_page_size - 1)); =20 /* --=20 2.43.0