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([71.212.136.242]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ea024ec723sm1484438a91.46.2024.11.14.08.01.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 08:01:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1731600105; x=1732204905; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=qWIXUHGQnTcdkm072yvGDVIoDbE1775WHviaFUbmmuU=; b=ovA8eWyTCJLl8iHhUBRmn93o83Eq2I4oEyHSNgLisnbg3WffO2OIvvhWs0N3LEZGcp +nntnn0adTEZ1UoPuh3EP9n+HgZ+scVffr+hGbkCuBijx4B6UMbyoxLvlRvGtzXIt0e5 YEHa/YR46Newt+2wdiI7pUslJSbH31ELw9qbZDE2H/oXnlOGswS9mXvI3Hu0EB6xxtLG OLXjMOngFlX/yDIJLgB+8DVY2ncqzmYI5qmS7ceS8u1rsUu8qrrG75GHC73JPrHx4lZU 5AuSl6T5+A5BQh+ZOPH84Vt6KzNl/N1ytmZ0hrhkVVWPf4CeN6FC4YaQaAYEsFRShiro 5QBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731600105; x=1732204905; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qWIXUHGQnTcdkm072yvGDVIoDbE1775WHviaFUbmmuU=; b=TYFb/kSYtvymoFeF2WCQaUs+a4z7v/qKFlkI+rOEDAEGzJVUN16rfX72XXZLB1erIE DCyt01bcRUegcflaPuqd6xxmNpwsC2UQJvO15dgOzGVdrxAUaTjmiFmDk8E5TY6ucmZH aR9r6LGZHwdtXt60Zg+ktVyb1sVHhdqmHhiM2vQ79be62MyV49fAks70M+3RbM3AmOW6 T0tTZcMQEzTzxZo9MD8iHTSuSYUr7T8wd8wA9q+7i2OON9F39GnbLf3KXCepNo/Pb443 n5T85nP8mAlBPTpChubC2Hu+lLSIqYfKdv5zYTq5mjZesYCkMKbV7jQiVOohUEK0XyJB 8RfA== X-Gm-Message-State: AOJu0YwG5JBPcDRFwKfSqnnr22rgv5/rUMA4pGI1anBzS5QNvohEMCxQ NtpFJumlOczIo4z9GvD2XqMzpcPI1f7jQ6uNAS09faYIGlnVEMZpmurv4aRawKEW0Uhc1plEiwT / X-Google-Smtp-Source: AGHT+IHPvPz14MAvO19icCcoybrM8ZtKp3yBE5tx84N/3/o3EC5HVEijtTtZIi2335BwNZMR67Pj6A== X-Received: by 2002:a17:90b:3883:b0:2e2:d3e1:f863 with SMTP id 98e67ed59e1d1-2e9b171e360mr33853299a91.12.1731600105146; Thu, 14 Nov 2024 08:01:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 17/54] accel/tcg: Replace victim_tlb_hit with tlbtree_hit Date: Thu, 14 Nov 2024 08:00:53 -0800 Message-ID: <20241114160131.48616-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241114160131.48616-1-richard.henderson@linaro.org> References: <20241114160131.48616-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731600729325116600 Content-Type: text/plain; charset="utf-8" Change from a linear search on the victim tlb to a balanced binary tree search on the interval tree. Signed-off-by: Richard Henderson Reviewed-by: Pierrick Bouvier --- accel/tcg/cputlb.c | 59 ++++++++++++++++++++++++---------------------- 1 file changed, 31 insertions(+), 28 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 3aab72ea82..ea4b78866b 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1384,35 +1384,38 @@ static void io_failed(CPUState *cpu, CPUTLBEntryFul= l *full, vaddr addr, } } =20 -/* Return true if ADDR is present in the victim tlb, and has been copied - back to the main tlb. */ -static bool victim_tlb_hit(CPUState *cpu, size_t mmu_idx, size_t index, - MMUAccessType access_type, vaddr addr) +/* + * Return true if ADDR is present in the interval tree, + * and has been copied back to the main tlb. + */ +static bool tlbtree_hit(CPUState *cpu, int mmu_idx, + MMUAccessType access_type, vaddr addr) { - size_t vidx; + CPUTLBDesc *desc =3D &cpu->neg.tlb.d[mmu_idx]; + CPUTLBDescFast *fast =3D &cpu->neg.tlb.f[mmu_idx]; + CPUTLBEntryTree *node; + size_t index; =20 assert_cpu_is_self(cpu); - for (vidx =3D 0; vidx < CPU_VTLB_SIZE; ++vidx) { - CPUTLBEntry *vtlb =3D &cpu->neg.tlb.d[mmu_idx].vtable[vidx]; - - if (tlb_hit(tlb_read_idx(vtlb, access_type), addr)) { - /* Found entry in victim tlb, swap tlb and iotlb. */ - CPUTLBEntry tmptlb, *tlb =3D &cpu->neg.tlb.f[mmu_idx].table[in= dex]; - - qemu_spin_lock(&cpu->neg.tlb.c.lock); - copy_tlb_helper_locked(&tmptlb, tlb); - copy_tlb_helper_locked(tlb, vtlb); - copy_tlb_helper_locked(vtlb, &tmptlb); - qemu_spin_unlock(&cpu->neg.tlb.c.lock); - - CPUTLBEntryFull *f1 =3D &cpu->neg.tlb.d[mmu_idx].fulltlb[index= ]; - CPUTLBEntryFull *f2 =3D &cpu->neg.tlb.d[mmu_idx].vfulltlb[vidx= ]; - CPUTLBEntryFull tmpf; - tmpf =3D *f1; *f1 =3D *f2; *f2 =3D tmpf; - return true; - } + node =3D tlbtree_lookup_addr(desc, addr); + if (!node) { + /* There is no cached mapping for this page. */ + return false; } - return false; + + if (!tlb_hit(tlb_read_idx(&node->copy, access_type), addr)) { + /* This access is not permitted. */ + return false; + } + + /* Install the cached entry. */ + index =3D tlbfast_index(fast, addr); + qemu_spin_lock(&cpu->neg.tlb.c.lock); + copy_tlb_helper_locked(&fast->table[index], &node->copy); + qemu_spin_unlock(&cpu->neg.tlb.c.lock); + + desc->fulltlb[index] =3D node->full; + return true; } =20 static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size, @@ -1453,7 +1456,7 @@ static int probe_access_internal(CPUState *cpu, vaddr= addr, CPUTLBEntryFull *full; =20 if (!tlb_hit(tlb_addr, addr)) { - if (!victim_tlb_hit(cpu, mmu_idx, index, access_type, addr)) { + if (!tlbtree_hit(cpu, mmu_idx, access_type, addr)) { if (!tlb_fill_align(cpu, addr, access_type, mmu_idx, 0, fault_size, nonfault, retaddr)) { /* Non-faulting page table read failed. */ @@ -1733,7 +1736,7 @@ static bool mmu_lookup1(CPUState *cpu, MMULookupPageD= ata *data, MemOp memop, =20 /* If the TLB entry is for a different page, reload and try again. */ if (!tlb_hit(tlb_addr, addr)) { - if (!victim_tlb_hit(cpu, mmu_idx, index, access_type, addr)) { + if (!tlbtree_hit(cpu, mmu_idx, access_type, addr)) { tlb_fill_align(cpu, addr, access_type, mmu_idx, memop, data->size, false, ra); maybe_resized =3D true; @@ -1912,7 +1915,7 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr a= ddr, MemOpIdx oi, /* Check TLB entry and enforce page permissions. */ flags =3D TLB_FLAGS_MASK; if (!tlb_hit(tlb_addr_write(tlbe), addr)) { - if (!victim_tlb_hit(cpu, mmu_idx, index, MMU_DATA_STORE, addr)) { + if (!tlbtree_hit(cpu, mmu_idx, MMU_DATA_STORE, addr)) { tlb_fill_align(cpu, addr, MMU_DATA_STORE, mmu_idx, mop, size, false, retaddr); did_tlb_fill =3D true; --=20 2.43.0