From nobody Sat Nov 23 18:42:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1731575782; cv=none; d=zohomail.com; s=zohoarc; b=cCwvez9CAej5ylcSjphF8jLV931MHBSG5q2y3fSBaGlYiNBSE3ZmPXxI/nkJcLwoctqA05EiTMPoh75e/6IWDx8LT2v3nJ/GBAiaKzLGE0nUOr0tQbyDASJWl2NpqaZNfJNlZWzBgK7tOJHwdHOBHqiQuFJhLT6am2i7bPOPLI4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1731575782; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rhsOIHC2GPGhTuIUOV5OrweCSoluniZqBwzjLjieyy0=; b=mkvbDhJueAX466gCl4k3+76tzIhKMAmCyLD0mE58xnR5CL+TVEePMZyS2VT/vDREfzOMxdKY7ewfUPLonpOl36xwuET2uBvNcCn8Pq8b8lOgC8XPwh6bHL7BhFtR0akicKnKfbfQzY2Bh75Y/eo8d2phXDI0dWzz9BUaa+iOJSQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1731575782796186.92550817275253; Thu, 14 Nov 2024 01:16:22 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBVw3-0000TG-Br; Thu, 14 Nov 2024 04:14:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBVvL-0008L8-H8 for qemu-devel@nongnu.org; Thu, 14 Nov 2024 04:14:00 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBVvH-0007iP-UV for qemu-devel@nongnu.org; Thu, 14 Nov 2024 04:13:59 -0500 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-37d49a7207cso243015f8f.0 for ; Thu, 14 Nov 2024 01:13:53 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3821ae313e3sm899050f8f.94.2024.11.14.01.13.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 01:13:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1731575632; x=1732180432; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rhsOIHC2GPGhTuIUOV5OrweCSoluniZqBwzjLjieyy0=; b=ORRTONr1iM4q7OQhDCpuftApwxYYSeb6rjvj/vtaiH4xFhptagunhFUxyzI77VW1yF epP1fcP9n8dA9gCvYh0ES2qKyVPqT5Bjx0K6DJyQN03E5gyZjGOmOiXzTnrfj16MVJZU +o/UOA06A6qXbhFZ8bqxw4AIZBWBpBbQ3JkBmVVfkrdxqmgd3wV4R/OaYNmsDjmfky70 2+cdkk+B6+RVf13dWK8ADi9nrB2NFr5spAd1cElVX+JrkoPZZ36psjRHR4hMtETiN61p QxKxofKB2SslIz4ZmORXJTpqxz8Vdens9U1GMes99eSIddoZ5jz0fPJDvV8etsdCbYBm jpXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731575632; x=1732180432; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rhsOIHC2GPGhTuIUOV5OrweCSoluniZqBwzjLjieyy0=; b=W46MgdsD1P2vRRQHif2kZHhT/PFNVms0NahEhdrJ+6//MTjgIxGW4USjROzGaFenZW fK4/VD6NLYAxJsx1/Mg89ZlL7nVc031ehpUNqLUncIVqgvd4uUUWbiGIgAjlXFFlPwNN ZFZgdrJMAzMchb5tRBDlqUW9aauhqhASNh7bNBUyWnIlsQTqt6ArnmoeUCWGivsExBZ0 ukPS0q9sNZ1KuGgPjIVuAC4Oc7GFHkb3YdL/3kVoUZzDsySWhc7MUWqLxS/PS12Kt7bD YmHwqRKVYkk+ZZnqvLmjT2aBXxr5xay07beD+FsuPBWvgXbY8ne/aim1BVB/wauqFuje WWlg== X-Forwarded-Encrypted: i=1; AJvYcCXZWUXgo3O3Na52so7/CqKTg7eYXvyQFQeGDIIi090eDmFTdDJCrEPsNeL9FtXKEp1e2DIFBCBpBU+1@nongnu.org X-Gm-Message-State: AOJu0YxW2gImJAFQK2JnIMTzXKVetIo11fGRzCacl4rLmPrJowV76R6Y a94J3YOBr6aA5F9LJ2i+el6703gv1UVUT/2LWckgeaeSPOeT926Rui/YXjX2yZA= X-Google-Smtp-Source: AGHT+IE1jEjtcZStucPGHvWfPm7tNwdJGb58mm7Ps0ze9doZWu8W46uB6Y6On+JLC/aJcdMpKFjHSQ== X-Received: by 2002:a05:6000:400c:b0:381:c7b7:706d with SMTP id ffacd0b85a97d-3821851c9c4mr1368506f8f.27.1731575632370; Thu, 14 Nov 2024 01:13:52 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ved Shanbhogue , Atish Patra , qemu-devel@nongnu.org Subject: [PATCH v5 8/9] target/riscv: Implement Smdbltrp behavior Date: Thu, 14 Nov 2024 10:13:29 +0100 Message-ID: <20241114091332.108811-9-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114091332.108811-1-cleger@rivosinc.com> References: <20241114091332.108811-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=cleger@rivosinc.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1731575784674116600 When the Smsdbltrp ISA extension is enabled, if a trap happens while MSTATUS.MDT is already set, it will trigger an abort or an NMI is the Smrnmi extension is available. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 52 +++++++++++++++++++++++++-------------- 1 file changed, 34 insertions(+), 18 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 623a3abbf7..8825572d5e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1703,6 +1703,17 @@ static target_ulong riscv_transformed_insn(CPURISCVS= tate *env, return xinsn; } =20 +static void riscv_do_nmi(CPURISCVState *env, target_ulong cause, bool virt) +{ + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_NMIE, false); + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_MNPV, virt); + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_MNPP, env->priv); + env->mncause =3D cause; + env->mnepc =3D env->pc; + env->pc =3D env->rnmi_irqvec; + riscv_cpu_set_mode(env, PRV_M, false); +} + /* * Handle Traps * @@ -1741,15 +1752,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool nnmi_excep =3D false; =20 if (cpu->cfg.ext_smrnmi && env->rnmip && async) { - env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_NMIE, false); - env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_MNPV, - env->virt_enabled); - env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_MNPP, - env->priv); - env->mncause =3D cause | ((target_ulong)1U << (TARGET_LONG_BITS - = 1)); - env->mnepc =3D env->pc; - env->pc =3D env->rnmi_irqvec; - riscv_cpu_set_mode(env, PRV_M, virt); + riscv_do_nmi(env, cause | ((target_ulong)1U << (TARGET_LONG_BITS -= 1)), + virt); return; } =20 @@ -1932,11 +1936,32 @@ void riscv_cpu_do_interrupt(CPUState *cs) /* Trapping to M mode, virt is disabled */ virt =3D false; } + /* + * If the hart encounters an exception while executing in M-mode, + * with the mnstatus.NMIE bit clear, the program counter is set to + * the RNMI exception trap handler address. + */ + nnmi_excep =3D cpu->cfg.ext_smrnmi && + !get_field(env->mnstatus, MNSTATUS_NMIE) && + !async; =20 s =3D env->mstatus; s =3D set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); s =3D set_field(s, MSTATUS_MPP, env->priv); s =3D set_field(s, MSTATUS_MIE, 0); + if (cpu->cfg.ext_smdbltrp) { + if (env->mstatus & MSTATUS_MDT) { + assert(env->priv =3D=3D PRV_M); + if (!cpu->cfg.ext_smrnmi || nnmi_excep) { + cpu_abort(CPU(cpu), "M-mode double trap\n"); + } else { + riscv_do_nmi(env, cause, false); + return; + } + } + + s =3D set_field(s, MSTATUS_MDT, 1); + } env->mstatus =3D s; mxlen =3D 16 << riscv_cpu_mxl(env); env->mcause =3D cause | ((target_ulong)async << (mxlen - 1)); @@ -1950,15 +1975,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mtval =3D tval; env->mtinst =3D tinst; =20 - /* - * If the hart encounters an exception while executing in M-mode, - * with the mnstatus.NMIE bit clear, the program counter is set to - * the RNMI exception trap handler address. - */ - nnmi_excep =3D cpu->cfg.ext_smrnmi && - !get_field(env->mnstatus, MNSTATUS_NMIE) && - !async; - if (nnmi_excep) { env->pc =3D env->rnmi_excpvec; } else { --=20 2.45.2