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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3821ae313e3sm899050f8f.94.2024.11.14.01.13.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 01:13:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1731575625; x=1732180425; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZuY5Yx+SDWSOTgPbmJ+N/i87adllxTARIGZlZIogOfA=; b=hZxqoGTypHP/ie0UMcE5++sECxT1ih3gugnbYYYCCY1834LlOEHYQ3KB9+cnfeIpTa dRp9brxzwHX9gcI40DxJJl9lf9Bdblq4lfOMOSznk7HG4SIMbEDzw6/14NN9x0i5Derh jMIWZfdE/6xCIe9ekqc32QzJE5LMFMIsOy085nfrbn3qyVcs4YoOX6PTR44WRq5QXRar ZLsb48CHobN9uST6iYWVvPXhLp1173b+0Zlq3mBWrTILNkS1zEr7tjE5I92Ffzd16T7J YunEWQ9Yasw9oZYfWCU3HPddro8V1bLbxWRq0iQTidnckb99fHk3WVexzvnrjwPrDMAU Lihw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731575625; x=1732180425; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZuY5Yx+SDWSOTgPbmJ+N/i87adllxTARIGZlZIogOfA=; b=vGPc+LlYcpq8+queqLBghmTCtD1xdMngnc3mmv0dE52L+CLGdQtlrGU3++n6Pgsd0h DQwTqJF00EIcRZTU9T9jQB+OMAtuU1CQ5BDq4GltJw5N+Tu+MDtTezQdXFlZhzOBEICz 5o2oNDK0GpoNLJg/skpBgbc0cuBhWePZLk6M15Xh8j9ifFd4lEOLQhjYb/kyAhnAUHPR i6ctBad2mk7w7FJvZsncXQ3ep3nT0f6vJSRgGroDNn4tWjDfKPdXJfbHrZ6d3XssZl82 sxb8/w6IrCuDyvWXpRleNU5T+/omLFhT6NeIqH4xnGQp/Z9VlVaQbL+vT+PvFt6W6HnU h6cg== X-Forwarded-Encrypted: i=1; AJvYcCUmRiy0Q3iGp3rnRDnqPXnglOhCf3VELIbuMdIOTdEzn7LSeQvCWWzkVD+tru2/afknpEuQNhkYg4L/@nongnu.org X-Gm-Message-State: AOJu0YxvZcOLtHKuzoHP9Co4l1CnwWCX6d3CS4PlLxUpU4cw0sko7b+5 Llm1uI1NrTqC5ebPYZnZMUAyFWHS1PfBQpuZZeWR60WZUvQ6wBITksKxoGdzgJs= X-Google-Smtp-Source: AGHT+IGWlkG+i1Di5LFaY3zZaQx5bJaRfuTnvv9w58/kgpBKwXbj5UGdBnVKcFgGGtZfqUUpjURo7w== X-Received: by 2002:a05:6000:178d:b0:37c:cfeb:e612 with SMTP id ffacd0b85a97d-3820df5bd38mr4840900f8f.1.1731575624714; Thu, 14 Nov 2024 01:13:44 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ved Shanbhogue , Atish Patra , qemu-devel@nongnu.org Subject: [PATCH v5 1/9] target/riscv: fix henvcfg potentially containing stale bits Date: Thu, 14 Nov 2024 10:13:22 +0100 Message-ID: <20241114091332.108811-2-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114091332.108811-1-cleger@rivosinc.com> References: <20241114091332.108811-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=cleger@rivosinc.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1731575648588116600 With the current implementation, if we had the current scenario: - set bit x in menvcfg - set bit x in henvcfg - clear bit x in menvcfg then, the internal variable env->henvcfg would still contain bit x due to both a wrong menvcfg mask used in write_henvcfg() as well as a missing update of henvcfg upon menvcfg update. This can lead to some wrong interpretation of the context. In order to update henvcfg upon menvcfg writing, call write_henvcfg() after writing menvcfg and fix the mask computation used in write_henvcfg() that is used to mesk env->menvcfg value (which could still lead to some stale bits). The same mechanism is also applied for henvcfgh writing. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- target/riscv/csr.c | 40 +++++++++++++++++++++++++++++++++++----- 1 file changed, 35 insertions(+), 5 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index b84b436151..73ac4d5449 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2345,6 +2345,8 @@ static RISCVException read_menvcfg(CPURISCVState *env= , int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException write_henvcfg(CPURISCVState *env, int csrno, + target_ulong val); static RISCVException write_menvcfg(CPURISCVState *env, int csrno, target_ulong val) { @@ -2357,6 +2359,7 @@ static RISCVException write_menvcfg(CPURISCVState *en= v, int csrno, (cfg->ext_svadu ? MENVCFG_ADUE : 0); } env->menvcfg =3D (env->menvcfg & ~mask) | (val & mask); + write_henvcfg(env, CSR_HENVCFG, env->henvcfg); =20 return RISCV_EXCP_NONE; } @@ -2368,6 +2371,8 @@ static RISCVException read_menvcfgh(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, + target_ulong val); static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, target_ulong val) { @@ -2378,6 +2383,7 @@ static RISCVException write_menvcfgh(CPURISCVState *e= nv, int csrno, uint64_t valh =3D (uint64_t)val << 32; =20 env->menvcfg =3D (env->menvcfg & ~mask) | (valh & mask); + write_henvcfgh(env, CSR_HENVCFGH, env->henvcfg >> 32); =20 return RISCV_EXCP_NONE; } @@ -2435,6 +2441,7 @@ static RISCVException write_henvcfg(CPURISCVState *en= v, int csrno, target_ulong val) { uint64_t mask =3D HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCF= G_CBZE; + uint64_t henvcfg_mask =3D mask, menvcfg_mask; RISCVException ret; =20 ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); @@ -2443,10 +2450,24 @@ static RISCVException write_henvcfg(CPURISCVState *= env, int csrno, } =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { - mask |=3D env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_A= DUE); + /* + * Since henvcfg depends on a menvcfg subset, we want to clear all= the + * menvcfg supported feature (whatever their state is) before enab= ling + * some new one using the provided value. Not doing so would resul= t in + * keeping stale menvcfg bits in henvcfg value if a bit was enable= d in + * menvcfg and then disabled before updating henvcfg for instance. + */ + menvcfg_mask =3D HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE; + mask |=3D env->menvcfg & menvcfg_mask; + henvcfg_mask |=3D menvcfg_mask; } =20 - env->henvcfg =3D (env->henvcfg & ~mask) | (val & mask); + /* + * 'henvcfg_mask' contains all supported bits (both in henvcfg and men= vcfg + * common bits) and 'mask' contains henvcfg exclusive bits as well as + * menvcfg enabled bits only. + */ + env->henvcfg =3D (env->henvcfg & ~henvcfg_mask) | (val & mask); =20 return RISCV_EXCP_NONE; } @@ -2469,8 +2490,13 @@ static RISCVException read_henvcfgh(CPURISCVState *e= nv, int csrno, static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, target_ulong val) { - uint64_t mask =3D env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | - HENVCFG_ADUE); + /* + * Same comment than the one in write_henvcfg() applies here, we want = to + * clear all previous menvcfg bits before enabling some new one to avo= id + * stale menvcfg bits in henvcfg. + */ + uint64_t henvcfg_mask =3D (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE= ); + uint64_t mask =3D env->menvcfg & henvcfg_mask; uint64_t valh =3D (uint64_t)val << 32; RISCVException ret; =20 @@ -2479,7 +2505,11 @@ static RISCVException write_henvcfgh(CPURISCVState *= env, int csrno, return ret; } =20 - env->henvcfg =3D (env->henvcfg & ~mask) | (valh & mask); + /* + * 'henvcfg_mask' contains all menvcfg supported bits and 'mask' conta= ins + * menvcfg enabled bits only. + */ + env->henvcfg =3D (env->henvcfg & ~henvcfg_mask) | (valh & mask); return RISCV_EXCP_NONE; } =20 --=20 2.45.2