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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3821ae313e3sm899050f8f.94.2024.11.14.01.13.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 01:13:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1731575625; x=1732180425; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZuY5Yx+SDWSOTgPbmJ+N/i87adllxTARIGZlZIogOfA=; b=hZxqoGTypHP/ie0UMcE5++sECxT1ih3gugnbYYYCCY1834LlOEHYQ3KB9+cnfeIpTa dRp9brxzwHX9gcI40DxJJl9lf9Bdblq4lfOMOSznk7HG4SIMbEDzw6/14NN9x0i5Derh jMIWZfdE/6xCIe9ekqc32QzJE5LMFMIsOy085nfrbn3qyVcs4YoOX6PTR44WRq5QXRar ZLsb48CHobN9uST6iYWVvPXhLp1173b+0Zlq3mBWrTILNkS1zEr7tjE5I92Ffzd16T7J YunEWQ9Yasw9oZYfWCU3HPddro8V1bLbxWRq0iQTidnckb99fHk3WVexzvnrjwPrDMAU Lihw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731575625; x=1732180425; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZuY5Yx+SDWSOTgPbmJ+N/i87adllxTARIGZlZIogOfA=; b=vGPc+LlYcpq8+queqLBghmTCtD1xdMngnc3mmv0dE52L+CLGdQtlrGU3++n6Pgsd0h DQwTqJF00EIcRZTU9T9jQB+OMAtuU1CQ5BDq4GltJw5N+Tu+MDtTezQdXFlZhzOBEICz 5o2oNDK0GpoNLJg/skpBgbc0cuBhWePZLk6M15Xh8j9ifFd4lEOLQhjYb/kyAhnAUHPR i6ctBad2mk7w7FJvZsncXQ3ep3nT0f6vJSRgGroDNn4tWjDfKPdXJfbHrZ6d3XssZl82 sxb8/w6IrCuDyvWXpRleNU5T+/omLFhT6NeIqH4xnGQp/Z9VlVaQbL+vT+PvFt6W6HnU h6cg== X-Forwarded-Encrypted: i=1; AJvYcCUmRiy0Q3iGp3rnRDnqPXnglOhCf3VELIbuMdIOTdEzn7LSeQvCWWzkVD+tru2/afknpEuQNhkYg4L/@nongnu.org X-Gm-Message-State: AOJu0YxvZcOLtHKuzoHP9Co4l1CnwWCX6d3CS4PlLxUpU4cw0sko7b+5 Llm1uI1NrTqC5ebPYZnZMUAyFWHS1PfBQpuZZeWR60WZUvQ6wBITksKxoGdzgJs= X-Google-Smtp-Source: AGHT+IGWlkG+i1Di5LFaY3zZaQx5bJaRfuTnvv9w58/kgpBKwXbj5UGdBnVKcFgGGtZfqUUpjURo7w== X-Received: by 2002:a05:6000:178d:b0:37c:cfeb:e612 with SMTP id ffacd0b85a97d-3820df5bd38mr4840900f8f.1.1731575624714; Thu, 14 Nov 2024 01:13:44 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ved Shanbhogue , Atish Patra , qemu-devel@nongnu.org Subject: [PATCH v5 1/9] target/riscv: fix henvcfg potentially containing stale bits Date: Thu, 14 Nov 2024 10:13:22 +0100 Message-ID: <20241114091332.108811-2-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114091332.108811-1-cleger@rivosinc.com> References: <20241114091332.108811-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=cleger@rivosinc.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1731575648588116600 With the current implementation, if we had the current scenario: - set bit x in menvcfg - set bit x in henvcfg - clear bit x in menvcfg then, the internal variable env->henvcfg would still contain bit x due to both a wrong menvcfg mask used in write_henvcfg() as well as a missing update of henvcfg upon menvcfg update. This can lead to some wrong interpretation of the context. In order to update henvcfg upon menvcfg writing, call write_henvcfg() after writing menvcfg and fix the mask computation used in write_henvcfg() that is used to mesk env->menvcfg value (which could still lead to some stale bits). The same mechanism is also applied for henvcfgh writing. Signed-off-by: Cl=C3=A9ment L=C3=A9ger --- target/riscv/csr.c | 40 +++++++++++++++++++++++++++++++++++----- 1 file changed, 35 insertions(+), 5 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index b84b436151..73ac4d5449 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2345,6 +2345,8 @@ static RISCVException read_menvcfg(CPURISCVState *env= , int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException write_henvcfg(CPURISCVState *env, int csrno, + target_ulong val); static RISCVException write_menvcfg(CPURISCVState *env, int csrno, target_ulong val) { @@ -2357,6 +2359,7 @@ static RISCVException write_menvcfg(CPURISCVState *en= v, int csrno, (cfg->ext_svadu ? MENVCFG_ADUE : 0); } env->menvcfg =3D (env->menvcfg & ~mask) | (val & mask); + write_henvcfg(env, CSR_HENVCFG, env->henvcfg); =20 return RISCV_EXCP_NONE; } @@ -2368,6 +2371,8 @@ static RISCVException read_menvcfgh(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, + target_ulong val); static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, target_ulong val) { @@ -2378,6 +2383,7 @@ static RISCVException write_menvcfgh(CPURISCVState *e= nv, int csrno, uint64_t valh =3D (uint64_t)val << 32; =20 env->menvcfg =3D (env->menvcfg & ~mask) | (valh & mask); + write_henvcfgh(env, CSR_HENVCFGH, env->henvcfg >> 32); =20 return RISCV_EXCP_NONE; } @@ -2435,6 +2441,7 @@ static RISCVException write_henvcfg(CPURISCVState *en= v, int csrno, target_ulong val) { uint64_t mask =3D HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCF= G_CBZE; + uint64_t henvcfg_mask =3D mask, menvcfg_mask; RISCVException ret; =20 ret =3D smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); @@ -2443,10 +2450,24 @@ static RISCVException write_henvcfg(CPURISCVState *= env, int csrno, } =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { - mask |=3D env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_A= DUE); + /* + * Since henvcfg depends on a menvcfg subset, we want to clear all= the + * menvcfg supported feature (whatever their state is) before enab= ling + * some new one using the provided value. Not doing so would resul= t in + * keeping stale menvcfg bits in henvcfg value if a bit was enable= d in + * menvcfg and then disabled before updating henvcfg for instance. + */ + menvcfg_mask =3D HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE; + mask |=3D env->menvcfg & menvcfg_mask; + henvcfg_mask |=3D menvcfg_mask; } =20 - env->henvcfg =3D (env->henvcfg & ~mask) | (val & mask); + /* + * 'henvcfg_mask' contains all supported bits (both in henvcfg and men= vcfg + * common bits) and 'mask' contains henvcfg exclusive bits as well as + * menvcfg enabled bits only. + */ + env->henvcfg =3D (env->henvcfg & ~henvcfg_mask) | (val & mask); =20 return RISCV_EXCP_NONE; } @@ -2469,8 +2490,13 @@ static RISCVException read_henvcfgh(CPURISCVState *e= nv, int csrno, static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, target_ulong val) { - uint64_t mask =3D env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE | - HENVCFG_ADUE); + /* + * Same comment than the one in write_henvcfg() applies here, we want = to + * clear all previous menvcfg bits before enabling some new one to avo= id + * stale menvcfg bits in henvcfg. + */ + uint64_t henvcfg_mask =3D (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE= ); + uint64_t mask =3D env->menvcfg & henvcfg_mask; uint64_t valh =3D (uint64_t)val << 32; RISCVException ret; =20 @@ -2479,7 +2505,11 @@ static RISCVException write_henvcfgh(CPURISCVState *= env, int csrno, return ret; } =20 - env->henvcfg =3D (env->henvcfg & ~mask) | (valh & mask); + /* + * 'henvcfg_mask' contains all menvcfg supported bits and 'mask' conta= ins + * menvcfg enabled bits only. + */ + env->henvcfg =3D (env->henvcfg & ~henvcfg_mask) | (valh & mask); return RISCV_EXCP_NONE; } =20 --=20 2.45.2 From nobody Sat Nov 23 17:10:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1731575761; cv=none; d=zohomail.com; s=zohoarc; b=TlcbwafD48y49b4FDjPNw8uW15FpJeBg8DUGAlN/EA3j+wQzT59PTlhcBqcHx59OJ6vlBMZswnYm0+4zQcTlCyU772oCAxcs32rVcyiw/BB5OOdSn0sdBVe9ymGAXeqR+NHKDgKNCygpKnXcRT5AeRE1kOWJIl00s0wH6mbln0A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1731575761; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=dLSaKTqtHeRWEFfzc/V24Z6g3ZeI+B7SMmaxUAKXCeg=; b=fTeuIwSd1pym+F85+wH6mrkdehcratTXAiybnh0iKj+b2R0po2C3TCoTpH6XTER7dYjdLmdyq1tfS28SyfasIumDqi/lcdtDkQDpmopzLiGRaFiOrmOreuNOjqZQUKxnwdJkY8huK5M2QZQRcg1f15vSlF9TFstRSWVjzk6smQE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1731575761116109.10772259061048; Thu, 14 Nov 2024 01:16:01 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBVvh-0008Rv-Mj; Thu, 14 Nov 2024 04:14:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBVvE-0008IS-TS for qemu-devel@nongnu.org; Thu, 14 Nov 2024 04:13:53 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBVv9-0007g7-Ca for qemu-devel@nongnu.org; Thu, 14 Nov 2024 04:13:49 -0500 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-37d4c1b1455so274186f8f.3 for ; Thu, 14 Nov 2024 01:13:47 -0800 (PST) Received: from carbon-x1.. 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Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 6 ++++ target/riscv/cpu_cfg.h | 1 + target/riscv/cpu_helper.c | 17 ++++++++++ target/riscv/csr.c | 70 +++++++++++++++++++++++++++++++++------ 5 files changed, 85 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 832556cc34..695de5667f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -553,6 +553,7 @@ void riscv_cpu_set_geilen(CPURISCVState *env, target_ul= ong geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); +bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt); G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t reta= ddr); diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 1a5200d1d5..08cc5b2e22 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -558,6 +558,7 @@ #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ #define MSTATUS_TW 0x00200000 /* since: priv-1.10 */ #define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */ +#define MSTATUS_SDT 0x01000000 #define MSTATUS_GVA 0x4000000000ULL #define MSTATUS_MPV 0x8000000000ULL =20 @@ -588,6 +589,7 @@ typedef enum { #define SSTATUS_XS 0x00018000 #define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */ #define SSTATUS_MXR 0x00080000 +#define SSTATUS_SDT 0x01000000 =20 #define SSTATUS64_UXL 0x0000000300000000ULL =20 @@ -777,11 +779,13 @@ typedef enum RISCVException { #define MENVCFG_CBIE (3UL << 4) #define MENVCFG_CBCFE BIT(6) #define MENVCFG_CBZE BIT(7) +#define MENVCFG_DTE (1ULL << 59) #define MENVCFG_ADUE (1ULL << 61) #define MENVCFG_PBMTE (1ULL << 62) #define MENVCFG_STCE (1ULL << 63) =20 /* For RV32 */ +#define MENVCFGH_DTE BIT(27) #define MENVCFGH_ADUE BIT(29) #define MENVCFGH_PBMTE BIT(30) #define MENVCFGH_STCE BIT(31) @@ -795,11 +799,13 @@ typedef enum RISCVException { #define HENVCFG_CBIE MENVCFG_CBIE #define HENVCFG_CBCFE MENVCFG_CBCFE #define HENVCFG_CBZE MENVCFG_CBZE +#define HENVCFG_DTE MENVCFG_DTE #define HENVCFG_ADUE MENVCFG_ADUE #define HENVCFG_PBMTE MENVCFG_PBMTE #define HENVCFG_STCE MENVCFG_STCE =20 /* For RV32 */ +#define HENVCFGH_DTE MENVCFGH_DTE #define HENVCFGH_ADUE MENVCFGH_ADUE #define HENVCFGH_PBMTE MENVCFGH_PBMTE #define HENVCFGH_STCE MENVCFGH_STCE diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 092744360e..518102d748 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -77,6 +77,7 @@ struct RISCVCPUConfig { bool ext_smstateen; bool ext_sstc; bool ext_smcntrpmf; + bool ext_ssdbltrp; bool ext_svadu; bool ext_svinval; bool ext_svnapot; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 648d4ed833..b9f36e8621 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -63,6 +63,19 @@ int riscv_env_mmu_index(CPURISCVState *env, bool ifetch) #endif } =20 +bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt) +{ +#ifdef CONFIG_USER_ONLY + return false; +#else + if (virt) { + return (env->henvcfg & HENVCFG_DTE) !=3D 0; + } else { + return (env->menvcfg & MENVCFG_DTE) !=3D 0; + } +#endif +} + void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, uint64_t *cs_base, uint32_t *pflags) { @@ -562,6 +575,10 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) =20 g_assert(riscv_has_ext(env, RVH)); =20 + if (riscv_env_smode_dbltrp_enabled(env, current_virt)) { + mstatus_mask |=3D MSTATUS_SDT; + } + if (current_virt) { /* Current V=3D1 and we are about to change to V=3D0 */ env->vsstatus =3D env->mstatus & mstatus_mask; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 73ac4d5449..054418ff54 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -540,6 +540,15 @@ static RISCVException aia_hmode32(CPURISCVState *env, = int csrno) return hmode32(env, csrno); } =20 +static RISCVException dbltrp_hmode(CPURISCVState *env, int csrno) +{ + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + return RISCV_EXCP_NONE; + } + + return hmode(env, csrno); +} + static RISCVException pmp(CPURISCVState *env, int csrno) { if (riscv_cpu_cfg(env)->pmp) { @@ -1600,6 +1609,13 @@ static RISCVException write_mstatus(CPURISCVState *e= nv, int csrno, mask |=3D MSTATUS_VS; } =20 + if (riscv_env_smode_dbltrp_enabled(env, env->virt_enabled)) { + mask |=3D MSTATUS_SDT; + if ((val & MSTATUS_SDT) !=3D 0) { + val &=3D ~MSTATUS_SIE; + } + } + if (xl !=3D MXL_RV32 || env->debugger) { if (riscv_has_ext(env, RVH)) { mask |=3D MSTATUS_MPV | MSTATUS_GVA; @@ -2356,7 +2372,11 @@ static RISCVException write_menvcfg(CPURISCVState *e= nv, int csrno, if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { mask |=3D (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) | - (cfg->ext_svadu ? MENVCFG_ADUE : 0); + (cfg->ext_svadu ? MENVCFG_ADUE : 0) | + (cfg->ext_ssdbltrp ? MENVCFG_DTE : 0); + if ((val & MENVCFG_DTE) =3D=3D 0) { + env->mstatus &=3D ~MSTATUS_SDT; + } } env->menvcfg =3D (env->menvcfg & ~mask) | (val & mask); write_henvcfg(env, CSR_HENVCFG, env->henvcfg); @@ -2379,9 +2399,14 @@ static RISCVException write_menvcfgh(CPURISCVState *= env, int csrno, const RISCVCPUConfig *cfg =3D riscv_cpu_cfg(env); uint64_t mask =3D (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) | - (cfg->ext_svadu ? MENVCFG_ADUE : 0); + (cfg->ext_svadu ? MENVCFG_ADUE : 0) | + (cfg->ext_ssdbltrp ? MENVCFG_DTE : 0); uint64_t valh =3D (uint64_t)val << 32; =20 + if ((valh & MENVCFG_DTE) =3D=3D 0) { + env->mstatus &=3D ~MSTATUS_SDT; + } + env->menvcfg =3D (env->menvcfg & ~mask) | (valh & mask); write_henvcfgh(env, CSR_HENVCFGH, env->henvcfg >> 32); =20 @@ -2431,9 +2456,10 @@ static RISCVException read_henvcfg(CPURISCVState *en= v, int csrno, * henvcfg.pbmte is read_only 0 when menvcfg.pbmte =3D 0 * henvcfg.stce is read_only 0 when menvcfg.stce =3D 0 * henvcfg.adue is read_only 0 when menvcfg.adue =3D 0 + * henvcfg.dte is read_only 0 when menvcfg.dte =3D 0 */ - *val =3D env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE= ) | - env->menvcfg); + *val =3D env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE= | + HENVCFG_DTE) | env->menvcfg); return RISCV_EXCP_NONE; } =20 @@ -2457,7 +2483,8 @@ static RISCVException write_henvcfg(CPURISCVState *en= v, int csrno, * keeping stale menvcfg bits in henvcfg value if a bit was enable= d in * menvcfg and then disabled before updating henvcfg for instance. */ - menvcfg_mask =3D HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE; + menvcfg_mask =3D HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE | + HENVCFG_DTE; mask |=3D env->menvcfg & menvcfg_mask; henvcfg_mask |=3D menvcfg_mask; } @@ -2468,6 +2495,9 @@ static RISCVException write_henvcfg(CPURISCVState *en= v, int csrno, * menvcfg enabled bits only. */ env->henvcfg =3D (env->henvcfg & ~henvcfg_mask) | (val & mask); + if ((env->henvcfg & HENVCFG_DTE) =3D=3D 0) { + env->vsstatus &=3D ~MSTATUS_SDT; + } =20 return RISCV_EXCP_NONE; } @@ -2482,8 +2512,8 @@ static RISCVException read_henvcfgh(CPURISCVState *en= v, int csrno, return ret; } =20 - *val =3D (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADU= E) | - env->menvcfg)) >> 32; + *val =3D (env->henvcfg & (~(HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADU= E | + HENVCFG_DTE) | env->menvcfg)) >> 32; return RISCV_EXCP_NONE; } =20 @@ -2495,7 +2525,8 @@ static RISCVException write_henvcfgh(CPURISCVState *e= nv, int csrno, * clear all previous menvcfg bits before enabling some new one to avo= id * stale menvcfg bits in henvcfg. */ - uint64_t henvcfg_mask =3D (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE= ); + uint64_t henvcfg_mask =3D (HENVCFG_PBMTE | HENVCFG_STCE | HENVCFG_ADUE= | + HENVCFG_DTE); uint64_t mask =3D env->menvcfg & henvcfg_mask; uint64_t valh =3D (uint64_t)val << 32; RISCVException ret; @@ -2504,12 +2535,15 @@ static RISCVException write_henvcfgh(CPURISCVState = *env, int csrno, if (ret !=3D RISCV_EXCP_NONE) { return ret; } - /* * 'henvcfg_mask' contains all menvcfg supported bits and 'mask' conta= ins * menvcfg enabled bits only. */ env->henvcfg =3D (env->henvcfg & ~henvcfg_mask) | (valh & mask); + if ((env->henvcfg & HENVCFG_DTE) =3D=3D 0) { + env->vsstatus &=3D ~MSTATUS_SDT; + } + return RISCV_EXCP_NONE; } =20 @@ -2937,6 +2971,9 @@ static RISCVException read_sstatus_i128(CPURISCVState= *env, int csrno, if (env->xl !=3D MXL_RV32 || env->debugger) { mask |=3D SSTATUS64_UXL; } + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + mask |=3D SSTATUS_SDT; + } =20 *val =3D int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus)); return RISCV_EXCP_NONE; @@ -2949,6 +2986,9 @@ static RISCVException read_sstatus(CPURISCVState *env= , int csrno, if (env->xl !=3D MXL_RV32 || env->debugger) { mask |=3D SSTATUS64_UXL; } + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + mask |=3D SSTATUS_SDT; + } /* TODO: Use SXL not MXL. */ *val =3D add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask); return RISCV_EXCP_NONE; @@ -2964,6 +3004,9 @@ static RISCVException write_sstatus(CPURISCVState *en= v, int csrno, mask |=3D SSTATUS64_UXL; } } + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + mask |=3D SSTATUS_SDT; + } target_ulong newval =3D (env->mstatus & ~mask) | (val & mask); return write_mstatus(env, CSR_MSTATUS, newval); } @@ -4069,6 +4112,13 @@ static RISCVException write_vsstatus(CPURISCVState *= env, int csrno, if ((val & VSSTATUS64_UXL) =3D=3D 0) { mask &=3D ~VSSTATUS64_UXL; } + if ((env->henvcfg & HENVCFG_DTE)) { + if ((val & SSTATUS_SDT) !=3D 0) { + val &=3D ~SSTATUS_SIE; + } + } else { + val &=3D ~SSTATUS_SDT; + } env->vsstatus =3D (env->vsstatus & ~mask) | (uint64_t)val; return RISCV_EXCP_NONE; } @@ -5276,7 +5326,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_VSATP] =3D { "vsatp", hmode, read_vsatp, write_v= satp, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, =20 - [CSR_MTVAL2] =3D { "mtval2", hmode, read_mtval2, write_m= tval2, + [CSR_MTVAL2] =3D { "mtval2", dbltrp_hmode, read_mtval2, write_mtv= al2, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, [CSR_MTINST] =3D { "mtinst", hmode, read_mtinst, write_m= tinst, .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, --=20 2.45.2 From nobody Sat Nov 23 17:10:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3821ae313e3sm899050f8f.94.2024.11.14.01.13.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 01:13:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1731575627; x=1732180427; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JwIuN+J3+bzup2NaOf8IKQF5a5sBeZ+ThACkLSBKsdk=; b=ktjc1JS2vTGXS1o/SYNGxLHL6KMdLxlBnEbr+ekVuqQj3ZRvQQ4sI7fI4tZH8096s5 NZb2FmHDTZJ6vf1nzbBi9lnqxOQbETlREErZxtXXH4SQ9t0I6/er4dOMLX/MPuLl48qu i5qyEnvJArDzYTdYGka8gvlRp6neY4R/NvQMf2KSCpbZE00E+IZGLpExq0kpfYw29iiV 8y0yCOK2Si/0RnlxbPcmzviKtRAbI6/qPfDCpgBO22Yc9isoNHmZNTu29rDZC7nsZrUX GwwY9DpNXtOsVfVfNWAyemByM6KdVVRJwP3j8MoGHKYNgHk0ay8qLpUh04sHuL9KhTSF MqnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731575627; x=1732180427; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JwIuN+J3+bzup2NaOf8IKQF5a5sBeZ+ThACkLSBKsdk=; b=RhJ9hCL+ngKnij+tKRaI5H618nB2EwQqSZ4Aj1PFQNtDd5l0tAVepELc3bbnCId4g9 7OFNC6UZqVsxsepDcXMjxaarny6Zw9l4PuOP9ybVXN5jOgjg8FZc0mH8tV4egNpBlQMo 0ZTVZ/Vfs8TY6jK6F8HXhoz+a17wKAr+f6fabeUPvxHwd2LlkH1mdk8Nh0+EumfgJG09 1BBCBbLICXHNE9bE8tCruJYLZmW4PY6mnjgLB78beo6k8P7k6POGOPs8IPBVm0AfHkjQ gZjX6eGgpxVBXMU0gPCjQNn5rgGmBsGpy34izWFYVwOwxr/MrEwHtaRYxg3R1S6fKjIy TueQ== X-Forwarded-Encrypted: i=1; AJvYcCXKAjjgnrCt3A4L5GPlIenoz6hJuvPh/eA6dqbyPwZIun1UBejZfwtDgSb2lRG3A6kOJNKU5SRhwY3P@nongnu.org X-Gm-Message-State: AOJu0YyDZxBJUdS6hlhhgqHkx9sCTgnYUPIOUNKej5eUtNBrOG0wfdOk flBFxEo6B3vXFAIjH0/ej8uiyUxbPCGqV4fCnfkwOyJl8ZtIPhwGKFTRDLKelhs= X-Google-Smtp-Source: AGHT+IG2QlQXLwSlFrWfUBOuz6VZJ2rI+ELe1TPnuRdPTlkw+gnDWl3BUF9BnNS18hECoSGMaBmpaQ== X-Received: by 2002:a05:6000:2b08:b0:382:1e06:fb0 with SMTP id ffacd0b85a97d-3821e0612ecmr316365f8f.56.1731575626746; Thu, 14 Nov 2024 01:13:46 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ved Shanbhogue , Atish Patra , qemu-devel@nongnu.org Subject: [PATCH v5 3/9] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior Date: Thu, 14 Nov 2024 10:13:24 +0100 Message-ID: <20241114091332.108811-4-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114091332.108811-1-cleger@rivosinc.com> References: <20241114091332.108811-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=cleger@rivosinc.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1731575806894116600 When the Ssdbltrp extension is enabled, SSTATUS.SDT field is cleared when executing sret. When executing mret/mnret, SSTATUS.SDT is cleared when returning to U, VS or VU and VSSTATUS.SDT is cleared when returning to VU from HS. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Alistair Francis --- target/riscv/op_helper.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 180886f32a..dabc74de39 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -287,6 +287,18 @@ target_ulong helper_sret(CPURISCVState *env) get_field(mstatus, MSTATUS_SPIE)); mstatus =3D set_field(mstatus, MSTATUS_SPIE, 1); mstatus =3D set_field(mstatus, MSTATUS_SPP, PRV_U); + + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + if (riscv_has_ext(env, RVH)) { + target_ulong prev_vu =3D get_field(env->hstatus, HSTATUS_SPV) = && + prev_priv =3D=3D PRV_U; + /* Returning to VU from HS, vsstatus.sdt =3D 0 */ + if (!env->virt_enabled && prev_vu) { + env->vsstatus =3D set_field(env->vsstatus, MSTATUS_SDT, 0); + } + } + mstatus =3D set_field(mstatus, MSTATUS_SDT, 0); + } if (env->priv_ver >=3D PRIV_VERSION_1_12_0) { mstatus =3D set_field(mstatus, MSTATUS_MPRV, 0); } @@ -297,7 +309,6 @@ target_ulong helper_sret(CPURISCVState *env) target_ulong hstatus =3D env->hstatus; =20 prev_virt =3D get_field(hstatus, HSTATUS_SPV); - hstatus =3D set_field(hstatus, HSTATUS_SPV, 0); =20 env->hstatus =3D hstatus; @@ -328,6 +339,22 @@ static void check_ret_from_m_mode(CPURISCVState *env, = target_ulong retpc, riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC()); } } +static target_ulong ssdbltrp_mxret(CPURISCVState *env, target_ulong mstatu= s, + target_ulong prev_priv, + target_ulong prev_virt) +{ + /* If returning to U, VS or VU, sstatus.sdt =3D 0 */ + if (prev_priv =3D=3D PRV_U || (prev_virt && + (prev_priv =3D=3D PRV_S || prev_priv =3D=3D PRV_U))) { + mstatus =3D set_field(mstatus, MSTATUS_SDT, 0); + /* If returning to VU, vsstatus.sdt =3D 0 */ + if (prev_virt && prev_priv =3D=3D PRV_U) { + env->vsstatus =3D set_field(env->vsstatus, MSTATUS_SDT, 0); + } + } + + return mstatus; +} =20 target_ulong helper_mret(CPURISCVState *env) { @@ -345,6 +372,9 @@ target_ulong helper_mret(CPURISCVState *env) mstatus =3D set_field(mstatus, MSTATUS_MPP, riscv_has_ext(env, RVU) ? PRV_U : PRV_M); mstatus =3D set_field(mstatus, MSTATUS_MPV, 0); + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + mstatus =3D ssdbltrp_mxret(env, mstatus, prev_priv, prev_virt); + } if ((env->priv_ver >=3D PRIV_VERSION_1_12_0) && (prev_priv !=3D PRV_M)= ) { mstatus =3D set_field(mstatus, MSTATUS_MPRV, 0); } @@ -378,6 +408,9 @@ target_ulong helper_mnret(CPURISCVState *env) if (prev_priv < PRV_M) { env->mstatus =3D set_field(env->mstatus, MSTATUS_MPRV, false); } + if (riscv_cpu_cfg(env)->ext_ssdbltrp) { + env->mstatus =3D ssdbltrp_mxret(env, env->mstatus, prev_priv, prev= _virt); + } =20 if (riscv_has_ext(env, RVH) && prev_virt) { riscv_cpu_swap_hypervisor_regs(env); --=20 2.45.2 From nobody Sat Nov 23 17:10:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1731575683; cv=none; d=zohomail.com; s=zohoarc; b=a9yKTyNroBJQ24v8SNcg+JB7fWFR+bX8xfEEjo/AOkZ3LVtq8QSbG/B6XSySkb5Ed4+jKpbjGcomp9pYM6NqM0sfL8s8CB8xWg1e78CsaLOYt3spS+hP3qzS5ASDw4+QBvIZz9x27OidFcn6o7GG/3GESbjz3tpPtgQD8f7BGag= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1731575683; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=LrHnbm7YgnU66uKTHzJZu4HQG8WvQGothThJWH82CJs=; b=U9cvaluzRjNSvKEYvRvRYme/96ierw21v1YjO9abG5g0QthKm7nALhsdyZknkcHH5ft28mlwTBZOpndKemSjF1gtEyNiYLKvugBD+B2uaojXqgqKtM7ts9g7IZbXi+zGoMFX2LexrwcCpy+jcg/iKxt95CVfSI0nkyRn4VpI6Ec= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1731575683663877.6131468828344; Thu, 14 Nov 2024 01:14:43 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBVvm-0008SY-Dd; Thu, 14 Nov 2024 04:14:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBVvE-0008IV-Tj for qemu-devel@nongnu.org; Thu, 14 Nov 2024 04:13:53 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBVvB-0007gs-QI for qemu-devel@nongnu.org; Thu, 14 Nov 2024 04:13:52 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-4315eeb2601so4790775e9.2 for ; Thu, 14 Nov 2024 01:13:49 -0800 (PST) Received: from carbon-x1.. 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Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 +- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 42 ++++++++++++++++++++++++++++++++++----- 3 files changed, 39 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fed64741d1..5224eb356d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -285,7 +285,7 @@ static const char * const riscv_excp_names[] =3D { "load_page_fault", "reserved", "store_page_fault", - "reserved", + "double_trap", "reserved", "reserved", "reserved", diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 08cc5b2e22..0d0f253fcb 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -699,6 +699,7 @@ typedef enum RISCVException { RISCV_EXCP_INST_PAGE_FAULT =3D 0xc, /* since: priv-1.10.0 */ RISCV_EXCP_LOAD_PAGE_FAULT =3D 0xd, /* since: priv-1.10.0 */ RISCV_EXCP_STORE_PAGE_FAULT =3D 0xf, /* since: priv-1.10.0 */ + RISCV_EXCP_DOUBLE_TRAP =3D 0x10, RISCV_EXCP_SW_CHECK =3D 0x12, /* since: priv-1.13.0 */ RISCV_EXCP_HW_ERR =3D 0x13, /* since: priv-1.13.0 */ RISCV_EXCP_INST_GUEST_PAGE_FAULT =3D 0x14, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b9f36e8621..623a3abbf7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1715,6 +1715,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) CPURISCVState *env =3D &cpu->env; bool virt =3D env->virt_enabled; bool write_gva =3D false; + bool vsmode_exc; uint64_t s; int mode; =20 @@ -1729,6 +1730,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) !(env->mip & (1 << cause)); bool vs_injected =3D env->hvip & (1 << cause) & env->hvien && !(env->mip & (1 << cause)); + bool smode_double_trap =3D false; + uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; target_ulong tval =3D 0; target_ulong tinst =3D 0; target_ulong htval =3D 0; @@ -1839,13 +1842,34 @@ void riscv_cpu_do_interrupt(CPUState *cs) mode =3D env->priv <=3D PRV_S && cause < 64 && (((deleg >> cause) & 1) || s_injected || vs_injected) ? PRV_S : PR= V_M; =20 + vsmode_exc =3D env->virt_enabled && (((hdeleg >> cause) & 1) || vs_inj= ected); + /* + * Check double trap condition only if already in S-mode and targeting + * S-mode + */ + if (cpu->cfg.ext_ssdbltrp && env->priv =3D=3D PRV_S && mode =3D=3D PRV= _S) { + bool dte =3D (env->menvcfg & MENVCFG_DTE) !=3D 0; + bool sdt =3D (env->mstatus & MSTATUS_SDT) !=3D 0; + /* In VS or HS */ + if (riscv_has_ext(env, RVH)) { + if (vsmode_exc) { + /* VS -> VS, use henvcfg instead of menvcfg*/ + dte =3D (env->henvcfg & HENVCFG_DTE) !=3D 0; + } else if (env->virt_enabled) { + /* VS -> HS, use mstatus_hs */ + sdt =3D (env->mstatus_hs & MSTATUS_SDT) !=3D 0; + } + } + smode_double_trap =3D dte && sdt; + if (smode_double_trap) { + mode =3D PRV_M; + } + } + if (mode =3D=3D PRV_S) { /* handle the trap in S-mode */ if (riscv_has_ext(env, RVH)) { - uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; - - if (env->virt_enabled && - (((hdeleg >> cause) & 1) || vs_injected)) { + if (vsmode_exc) { /* Trap to VS mode */ /* * See if we need to adjust cause. Yes if its VS mode inte= rrupt @@ -1878,6 +1902,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) s =3D set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); s =3D set_field(s, MSTATUS_SPP, env->priv); s =3D set_field(s, MSTATUS_SIE, 0); + if (riscv_env_smode_dbltrp_enabled(env, virt)) { + s =3D set_field(s, MSTATUS_SDT, 1); + } env->mstatus =3D s; sxlen =3D 16 << riscv_cpu_sxl(env); env->scause =3D cause | ((target_ulong)async << (sxlen - 1)); @@ -1913,9 +1940,14 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mstatus =3D s; mxlen =3D 16 << riscv_cpu_mxl(env); env->mcause =3D cause | ((target_ulong)async << (mxlen - 1)); + if (smode_double_trap) { + env->mtval2 =3D env->mcause; + env->mcause =3D RISCV_EXCP_DOUBLE_TRAP; + } else { + env->mtval2 =3D mtval2; + } env->mepc =3D env->pc; env->mtval =3D tval; - env->mtval2 =3D mtval2; env->mtinst =3D tinst; =20 /* --=20 2.45.2 From nobody Sat Nov 23 17:10:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1731575727; cv=none; d=zohomail.com; s=zohoarc; b=mG4UHyqvSPexFr/n7jXDEtzvgKiFwbpMEwHkuk8cAih8aDE8QNgttZDwRbopNe0C1EVGsFKOF/3hF2nX+XMVDtKZoCMTb3PB+1yojt2oAfdO6oVLLM+Aua9u0e8y4WExQCd+P3Sk/jatBehw4S57gKwVs2+Fy2IamQdYM8D4QTg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1731575727; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=pPcEE6kBtAUoaXinJQfR30MxYrRluNtCFG7wXxXLjDk=; b=YMob1DxQsEXqOSYzndIrnn+6Q3O2aUfqQ8y1w7S59Yp3QCYTBtorNoBYxBs5GK3MSvn4ohpMtWY1ABoF3z4KXbTPh2qxYXq4i87cTDYmG+NzTi6hSGba1qPjBEUcDKwzFQxFUAi8G1cSSmgW09qjXypnTgrrQ2i6VPhwwOHLSM0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1731575726929485.14128277716964; Thu, 14 Nov 2024 01:15:26 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBVvz-0000Mu-Po; Thu, 14 Nov 2024 04:14:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBVvG-0008JP-Nv for qemu-devel@nongnu.org; Thu, 14 Nov 2024 04:13:55 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBVvE-0007hD-E3 for qemu-devel@nongnu.org; Thu, 14 Nov 2024 04:13:53 -0500 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-4315e62afe0so3885835e9.1 for ; Thu, 14 Nov 2024 01:13:50 -0800 (PST) Received: from carbon-x1.. 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Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5224eb356d..39555364bf 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -190,6 +190,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), + ISA_EXT_DATA_ENTRY(ssdbltrp, PRIV_VERSION_1_13_0, ext_ssdbltrp), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), @@ -1506,6 +1507,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { MULTI_EXT_CFG_BOOL("smrnmi", ext_smrnmi, false), MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), MULTI_EXT_CFG_BOOL("ssaia", ext_ssaia, false), + MULTI_EXT_CFG_BOOL("ssdbltrp", ext_ssdbltrp, false), MULTI_EXT_CFG_BOOL("svade", ext_svade, false), MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true), MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false), --=20 2.45.2 From nobody Sat Nov 23 17:10:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1731575714; cv=none; d=zohomail.com; s=zohoarc; b=chgAm3YQUSK3TQyRyBvglqnip5UMt2SOWwxgxxLxRann+I7UuYw8+Z3URu2KhDyWwNB43gpRaWGwj71P4RzRiESFbE1FymPt+IlFii8YojVRVEbNpACnFqqX0CZf3uPmLaYQu3WcY2e3qpW/MOIYJML+I4+b+FE1ihfYiCmp8XY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1731575714; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=/WxMvHkEFShTB/KP6SbLDpruZLu+ZNC+8yWnih7w6xQ=; b=GC3YOYGUAWFYtAOypSJyeGiBxszCFBXy9Osst0fz0tcA5XkALxfqJjalGcmNbq1fWaPIvmLZ1pDbtvyhOaeEjuiwk8b5v+wb+fHn9B0QikR+m2Yh1jhqpKLm3JwPCd3SFup2+6dpqZQ5tMw7VSoQhUJ5Rz1rzz7IX5Z85vVf4pg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1731575714801424.8781385020146; Thu, 14 Nov 2024 01:15:14 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBVw0-0000Ov-Qh; Thu, 14 Nov 2024 04:14:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBVvI-0008Jx-Rr for qemu-devel@nongnu.org; Thu, 14 Nov 2024 04:13:57 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBVvE-0007hU-KQ for qemu-devel@nongnu.org; Thu, 14 Nov 2024 04:13:55 -0500 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-431481433bdso3421735e9.3 for ; Thu, 14 Nov 2024 01:13:51 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3821ae313e3sm899050f8f.94.2024.11.14.01.13.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 01:13:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1731575630; x=1732180430; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/WxMvHkEFShTB/KP6SbLDpruZLu+ZNC+8yWnih7w6xQ=; b=k21UX+FMQLeeXO/IYEF7pbgcSckAkUiM0IWCPeYO2MrGlzwRiuQ9bgCLWor3yAn1La M6g5k2rywzo1iuDmTFs9O0jD6cXGWk9X75P3Fzb7tMgQQQxsy7bMeCZCNdH6Yc1CwwNI P+xRQHToZ3QVq3lrekPnAmPIyfWMWVf4ktMpZ0CZPnxusyqkkvKhnd2JRKjIH5i6DZrs 9SBInX7DaMqsOIuL3nkf98behTr6iwtz2/nMExkGQ1XfeV95WaRqmlSusfHb5oEp3HAH p3XNJtgpfcwTsXsAPWKtUl3N6eoQfHpFBv0TWEUA4+ZzIUa/2QvODmS7ei7o9jxH6Q0t BxSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731575630; x=1732180430; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/WxMvHkEFShTB/KP6SbLDpruZLu+ZNC+8yWnih7w6xQ=; b=HCpdBNHCfOSLdDlDgCqclNIw/XFzlWDKpGSRXbH/8RCpuP7/wdcJMcTgAok4zq7H+d QgjOvuzMicEdjUcs9wr+aouOe/uTWbu7N8346trzyrrb6fo/d+sGGxax6y9EAz1WWeMq boblaThqfUJdM/qjCd+6Gw523g2YDZ9ZwmRLENfQbhqsnyN6DlljTYXvj0OkDsU/dSUR J3G9a9yx6edNjBfoIG8jSRt0WtP+bC6x3eimqdOhUBwvh9l9EEo1Jl3ML17ZQfM5P4FF b0a+blRFkmme1EyyC+LfmLJ3HRXHHyHXVzddEqF6bthwsQw+7Uo22Bj0GFec8KGj1rUD PnAQ== X-Forwarded-Encrypted: i=1; AJvYcCVYzt/hzsuLao1Nw2CRNrdaqFayP8nX0mE3hctLTzRzHC7jc550n6PlsiX0Hwl+01Or2Ib1lzRCLKhw@nongnu.org X-Gm-Message-State: AOJu0YwAZSJ9eJGbEfxIzfVb58wmQ6mvQFOaVmWpIfsdS7bafNGAA94j nHwu/OWIoOAODyAvwOUn7AqJb2dmweVC6TUEulTJ9oymO7FB7tbursMet1PVEYA= X-Google-Smtp-Source: AGHT+IG8EGC9kzhwVnju/Dw0QWh3j2+EFMCeXpE1qe0U8y1wqdn7A4TAutIRujqEZdoNC1uyzUPf2A== X-Received: by 2002:a05:6000:42c2:b0:382:1478:1a04 with SMTP id ffacd0b85a97d-38214781a12mr1468626f8f.35.1731575630322; Thu, 14 Nov 2024 01:13:50 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ved Shanbhogue , Atish Patra , qemu-devel@nongnu.org Subject: [PATCH v5 6/9] target/riscv: Add Smdbltrp CSRs handling Date: Thu, 14 Nov 2024 10:13:27 +0100 Message-ID: <20241114091332.108811-7-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114091332.108811-1-cleger@rivosinc.com> References: <20241114091332.108811-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=cleger@rivosinc.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1731575716579116600 Add `ext_smdbltrp`in RISCVCPUConfig and implement MSTATUS.MDT behavior. Also set MDT to 1 at reset according to the specification. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 +++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_cfg.h | 1 + target/riscv/csr.c | 13 +++++++++++++ 4 files changed, 18 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 39555364bf..15b21e4f7d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -959,6 +959,9 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType= type) env->mstatus_hs =3D set_field(env->mstatus_hs, MSTATUS64_UXL, env->misa_mxl); } + if (riscv_cpu_cfg(env)->ext_smdbltrp) { + env->mstatus =3D set_field(env->mstatus, MSTATUS_MDT, 1); + } } env->mcause =3D 0; env->miclaim =3D MIP_SGEIP; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 0d0f253fcb..b368e27ca0 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -561,6 +561,7 @@ #define MSTATUS_SDT 0x01000000 #define MSTATUS_GVA 0x4000000000ULL #define MSTATUS_MPV 0x8000000000ULL +#define MSTATUS_MDT 0x40000000000ULL /* Smdbltrp extension */ =20 #define MSTATUS64_UXL 0x0000000300000000ULL #define MSTATUS64_SXL 0x0000000C00000000ULL diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 518102d748..8ac1e7fce3 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -78,6 +78,7 @@ struct RISCVCPUConfig { bool ext_sstc; bool ext_smcntrpmf; bool ext_ssdbltrp; + bool ext_smdbltrp; bool ext_svadu; bool ext_svinval; bool ext_svnapot; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 054418ff54..1ac5731d32 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1616,6 +1616,13 @@ static RISCVException write_mstatus(CPURISCVState *e= nv, int csrno, } } =20 + if (riscv_cpu_cfg(env)->ext_smdbltrp) { + mask |=3D MSTATUS_MDT; + if ((val & MSTATUS_MDT) !=3D 0) { + val &=3D ~MSTATUS_MIE; + } + } + if (xl !=3D MXL_RV32 || env->debugger) { if (riscv_has_ext(env, RVH)) { mask |=3D MSTATUS_MPV | MSTATUS_GVA; @@ -1654,6 +1661,12 @@ static RISCVException write_mstatush(CPURISCVState *= env, int csrno, uint64_t valh =3D (uint64_t)val << 32; uint64_t mask =3D riscv_has_ext(env, RVH) ? MSTATUS_MPV | MSTATUS_GVA = : 0; =20 + if (riscv_cpu_cfg(env)->ext_smdbltrp) { + mask |=3D MSTATUS_MDT; + if ((valh & MSTATUS_MDT) !=3D 0) { + mask |=3D MSTATUS_MIE; + } + } env->mstatus =3D (env->mstatus & ~mask) | (valh & mask); =20 return RISCV_EXCP_NONE; --=20 2.45.2 From nobody Sat Nov 23 17:10:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1731575748; cv=none; d=zohomail.com; s=zohoarc; b=MT1HbrBpAHvjMfu+BlqjmFb5x9Pqp8qi8OhFMLZo9KuUFTdGHonDmRfCN+FDJweKXTJnHciLnZ9+FhVW+9VFJMkMI+/u5UYkU4Y+Yh2/M39xdQw8cAw5npB8kMblmr8TZKzK+apSTdyjqTHanjEapEqqmrwJd0aZuupaNnhkIrA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1731575748; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=e5VCSEROfFnSITFRhmQ5Rm5Z+/eZKzb7VObh38bI74M=; b=GDVYse8noQ/1wjgA73fiZZNE9hYvJDvr3nT9i9HO6NHkIWjdzMfoIgchYU3FlcmyXuk7AKH43iZsbp6S8K/yTQuM5lf/gtv2lW96aDu5AFU2YQ1/BKm2NUz8D1OQU+baycA3xvH1V+x0NqM21bEODz2lr5DLD/EYvXQzIHJiXPM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1731575748145559.6770517600916; Thu, 14 Nov 2024 01:15:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBVvp-000087-U0; Thu, 14 Nov 2024 04:14:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBVvL-0008L7-Gj for qemu-devel@nongnu.org; Thu, 14 Nov 2024 04:14:00 -0500 Received: from mail-lf1-x12b.google.com ([2a00:1450:4864:20::12b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBVvG-0007hm-GI for qemu-devel@nongnu.org; Thu, 14 Nov 2024 04:13:59 -0500 Received: by mail-lf1-x12b.google.com with SMTP id 2adb3069b0e04-53da3545908so358642e87.1 for ; Thu, 14 Nov 2024 01:13:52 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3821ae313e3sm899050f8f.94.2024.11.14.01.13.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 01:13:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1731575631; x=1732180431; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e5VCSEROfFnSITFRhmQ5Rm5Z+/eZKzb7VObh38bI74M=; b=3C6HlX6w7ygZCpKvl1Q+a+cusabPmMNdqkmR2VOngn0d3QW4oMQt3uht8J1ncVspoo h4oe0nwXSCfr3NC7Q0bhe8pE3/Kh1RiIDBLAR9VtW0KuOvOp6gjly/jNPE/sWukyn3Y8 b7CGIsoQFWbT7TvKhfiDdIWGvEPsLT+DW8VBbIcdeprDCjxA+Xgkl6F6lkiJ5GoRY8NH /0vNwHN2EDt0NOaxM3iID30t3nsfnzFT7je9ox9ddUZI5Pm1SOYxn6UYvSLLcJP8AINR g867SwD6UGqK4ullj0qkDhU5VPv36j6o4JpSrJjj0nvOTSFBmnEfTZmMPgnE0EDf876U kZOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731575631; x=1732180431; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e5VCSEROfFnSITFRhmQ5Rm5Z+/eZKzb7VObh38bI74M=; b=eiYJpNnP+Cq+HIXqrlYWZkHHPkgtxnoOT5lYI5v0tBMFaTbViY1NPX9VXSAoNFjbnp Rr/anx7xWlRGg5hg+/JZNDZgjiJpepv4QsN7yPdIARfvGuOUTmTjtlrP7t9jvLrZixFw 46xOjH3LTOTNoDlYDIFWWboYLUk5z4bQpoISjGkSkpii+Vf6WjcWgc7OPDKjPYdjaEvZ NmxkCrjuRvt1JJI7bNPu9rQ4VFhJa8qWi8emz935RiQEjgP4vqr1H6P/hdRoKDPGCiRe FRhm5Inz6RcV4KrvB/nWGzYsIlcIOODUHYY7Yp0q7eNKiWGneFXlb7JJeB3qEg9uJ3Ad am3A== X-Forwarded-Encrypted: i=1; AJvYcCUwwUQ5lq/UYKGzQnGMeVWgx0ETpCV3CJ/ffkBAw2SwDXUUnvtPjjtdaMREqhbwD8M/jsfzuiyzQrBm@nongnu.org X-Gm-Message-State: AOJu0Yy4uzJ361mG0W76Mg76yKnS2Rik7qtnIgkW9wMTOYsR6kmxMw5Q aAn4oeVaxZyAKVqj2Z2hlrZULZA7Nx25bjNMJaCDV4zUnXurEDsBoW86YkPXWwQ= X-Google-Smtp-Source: AGHT+IF1OJfD8iGL+A6cQediE5Vks/yi+m1EhKBEvVOF7+doo9vYEKH0yxEhEaiQo1UrKP7M6X97Qg== X-Received: by 2002:a05:6512:3e02:b0:539:8fcd:510 with SMTP id 2adb3069b0e04-53da5c44f67mr632759e87.20.1731575631322; Thu, 14 Nov 2024 01:13:51 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ved Shanbhogue , Atish Patra , qemu-devel@nongnu.org Subject: [PATCH v5 7/9] target/riscv: Implement Smdbltrp sret, mret and mnret behavior Date: Thu, 14 Nov 2024 10:13:28 +0100 Message-ID: <20241114091332.108811-8-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114091332.108811-1-cleger@rivosinc.com> References: <20241114091332.108811-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12b; envelope-from=cleger@rivosinc.com; helo=mail-lf1-x12b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1731575748507116600 When the Ssdbltrp extension is enabled, SSTATUS.MDT field is cleared when executing sret if executed in M-mode. When executing mret/mnret, SSTATUS.MDT is cleared. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Alistair Francis --- target/riscv/op_helper.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index dabc74de39..e5e10f7162 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -299,6 +299,9 @@ target_ulong helper_sret(CPURISCVState *env) } mstatus =3D set_field(mstatus, MSTATUS_SDT, 0); } + if (riscv_cpu_cfg(env)->ext_smdbltrp && env->priv >=3D PRV_M) { + mstatus =3D set_field(mstatus, MSTATUS_MDT, 0); + } if (env->priv_ver >=3D PRIV_VERSION_1_12_0) { mstatus =3D set_field(mstatus, MSTATUS_MPRV, 0); } @@ -375,6 +378,9 @@ target_ulong helper_mret(CPURISCVState *env) if (riscv_cpu_cfg(env)->ext_ssdbltrp) { mstatus =3D ssdbltrp_mxret(env, mstatus, prev_priv, prev_virt); } + if (riscv_cpu_cfg(env)->ext_smdbltrp) { + mstatus =3D set_field(mstatus, MSTATUS_MDT, 0); + } if ((env->priv_ver >=3D PRIV_VERSION_1_12_0) && (prev_priv !=3D PRV_M)= ) { mstatus =3D set_field(mstatus, MSTATUS_MPRV, 0); } @@ -412,6 +418,12 @@ target_ulong helper_mnret(CPURISCVState *env) env->mstatus =3D ssdbltrp_mxret(env, env->mstatus, prev_priv, prev= _virt); } =20 + if (riscv_cpu_cfg(env)->ext_smdbltrp) { + if (prev_priv < PRV_M) { + env->mstatus =3D set_field(env->mstatus, MSTATUS_MDT, 0); + } + } + if (riscv_has_ext(env, RVH) && prev_virt) { riscv_cpu_swap_hypervisor_regs(env); } --=20 2.45.2 From nobody Sat Nov 23 17:10:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1731575782; cv=none; d=zohomail.com; s=zohoarc; b=cCwvez9CAej5ylcSjphF8jLV931MHBSG5q2y3fSBaGlYiNBSE3ZmPXxI/nkJcLwoctqA05EiTMPoh75e/6IWDx8LT2v3nJ/GBAiaKzLGE0nUOr0tQbyDASJWl2NpqaZNfJNlZWzBgK7tOJHwdHOBHqiQuFJhLT6am2i7bPOPLI4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1731575782; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rhsOIHC2GPGhTuIUOV5OrweCSoluniZqBwzjLjieyy0=; b=mkvbDhJueAX466gCl4k3+76tzIhKMAmCyLD0mE58xnR5CL+TVEePMZyS2VT/vDREfzOMxdKY7ewfUPLonpOl36xwuET2uBvNcCn8Pq8b8lOgC8XPwh6bHL7BhFtR0akicKnKfbfQzY2Bh75Y/eo8d2phXDI0dWzz9BUaa+iOJSQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1731575782796186.92550817275253; Thu, 14 Nov 2024 01:16:22 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tBVw3-0000TG-Br; Thu, 14 Nov 2024 04:14:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tBVvL-0008L8-H8 for qemu-devel@nongnu.org; Thu, 14 Nov 2024 04:14:00 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1tBVvH-0007iP-UV for qemu-devel@nongnu.org; Thu, 14 Nov 2024 04:13:59 -0500 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-37d49a7207cso243015f8f.0 for ; Thu, 14 Nov 2024 01:13:53 -0800 (PST) Received: from carbon-x1.. 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Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 52 +++++++++++++++++++++++++-------------- 1 file changed, 34 insertions(+), 18 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 623a3abbf7..8825572d5e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1703,6 +1703,17 @@ static target_ulong riscv_transformed_insn(CPURISCVS= tate *env, return xinsn; } =20 +static void riscv_do_nmi(CPURISCVState *env, target_ulong cause, bool virt) +{ + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_NMIE, false); + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_MNPV, virt); + env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_MNPP, env->priv); + env->mncause =3D cause; + env->mnepc =3D env->pc; + env->pc =3D env->rnmi_irqvec; + riscv_cpu_set_mode(env, PRV_M, false); +} + /* * Handle Traps * @@ -1741,15 +1752,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool nnmi_excep =3D false; =20 if (cpu->cfg.ext_smrnmi && env->rnmip && async) { - env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_NMIE, false); - env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_MNPV, - env->virt_enabled); - env->mnstatus =3D set_field(env->mnstatus, MNSTATUS_MNPP, - env->priv); - env->mncause =3D cause | ((target_ulong)1U << (TARGET_LONG_BITS - = 1)); - env->mnepc =3D env->pc; - env->pc =3D env->rnmi_irqvec; - riscv_cpu_set_mode(env, PRV_M, virt); + riscv_do_nmi(env, cause | ((target_ulong)1U << (TARGET_LONG_BITS -= 1)), + virt); return; } =20 @@ -1932,11 +1936,32 @@ void riscv_cpu_do_interrupt(CPUState *cs) /* Trapping to M mode, virt is disabled */ virt =3D false; } + /* + * If the hart encounters an exception while executing in M-mode, + * with the mnstatus.NMIE bit clear, the program counter is set to + * the RNMI exception trap handler address. + */ + nnmi_excep =3D cpu->cfg.ext_smrnmi && + !get_field(env->mnstatus, MNSTATUS_NMIE) && + !async; =20 s =3D env->mstatus; s =3D set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); s =3D set_field(s, MSTATUS_MPP, env->priv); s =3D set_field(s, MSTATUS_MIE, 0); + if (cpu->cfg.ext_smdbltrp) { + if (env->mstatus & MSTATUS_MDT) { + assert(env->priv =3D=3D PRV_M); + if (!cpu->cfg.ext_smrnmi || nnmi_excep) { + cpu_abort(CPU(cpu), "M-mode double trap\n"); + } else { + riscv_do_nmi(env, cause, false); + return; + } + } + + s =3D set_field(s, MSTATUS_MDT, 1); + } env->mstatus =3D s; mxlen =3D 16 << riscv_cpu_mxl(env); env->mcause =3D cause | ((target_ulong)async << (mxlen - 1)); @@ -1950,15 +1975,6 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mtval =3D tval; env->mtinst =3D tinst; =20 - /* - * If the hart encounters an exception while executing in M-mode, - * with the mnstatus.NMIE bit clear, the program counter is set to - * the RNMI exception trap handler address. - */ - nnmi_excep =3D cpu->cfg.ext_smrnmi && - !get_field(env->mnstatus, MNSTATUS_NMIE) && - !async; - if (nnmi_excep) { env->pc =3D env->rnmi_excpvec; } else { --=20 2.45.2 From nobody Sat Nov 23 17:10:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3821ae313e3sm899050f8f.94.2024.11.14.01.13.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 01:13:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1731575633; x=1732180433; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zrlqhZAuqzC1HZX4nAGhxZk3V5yhPYxnlkqSF+GjVbk=; b=FGgYjlOddPJmjmGg2ut5zlvqjzsQcmOIYrUhhZBWiBH2U2YeO7ZeAtK7ixQL/vI1wx 1ZIsJqTqazyZNi4MEiajsjlByO+ffuMsFkhBTQyaC5F5t/kI3Sd06d97Opnu4t0aMv2e 8kTdGAn6/ydQJXJVq/LFfnQSVDHH1GAKocm2Pj97Xs34FWIBFaLLQ6+BXcEpMA8YrenT qFzYcLbfwAQ59a9LskAIvGLtctWeSW6MmDk1gURAoPvctsyEJu0aRj8mLerxoFsdF39p jIX7Bo2s+Uzzgwce1MSeZ6wR5C1RHnSorRzH/ULeHqfxjfVKqEfP7dng48rquVVsl5BM UDxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731575633; x=1732180433; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zrlqhZAuqzC1HZX4nAGhxZk3V5yhPYxnlkqSF+GjVbk=; b=DJEk41hnrvLXhLDMAXr3bwlurwUpWBaX9qGVsXPR2SMtrd+T4xVbdlfSMsrDboalNY YqpXjIz74/h27OwTe49LDLCw3YcklIIw6A0gSnnWZM23qxDpkM/b0DgZFgpnt9+l6LQr mByu0v5eS0W41qSHYtMi6jdZIHb4jVY5FrPkM4K7WJJzWJO++pXS0p+zntjBFnIkkDGi oro+zFsOqXVqdbRdPUGJy/2v1tyHynn5zb9RMM7p1YuIW5tG606JdPwrQrJ1y0gQp/xF OvpnuleDR6hmEiOmtHauuLmrPo/HbamUfK+iYlWricf+mllA+VrCP6U6G0j9qsGER1NM 9iJw== X-Forwarded-Encrypted: i=1; AJvYcCWLGfHgml/KqqjJB2TvniA7fUGzyTp8193SUfbwf7GihKOxUgb97r0IeiOZNGnQ2uph9bVLTTF9mVF5@nongnu.org X-Gm-Message-State: AOJu0YwH2DWQwnsH8Plsx0ngI5WW0Yxh5ksL3MuU98DV89nxwG7+2g9y 2qywWgUotDJh2tK7C0Ysfw4YmFhqsGBOLilos70hRmE7NBzUzSiSe2cqecIZ5yo= X-Google-Smtp-Source: AGHT+IFTA47yr4OmHfm+XxAgY9/A2HkbedU2UAoVuiALpJy1/jtwze+NZySWxDEDuSKh5uy6PTOcHA== X-Received: by 2002:a5d:59a3:0:b0:37d:4fe9:b6a6 with SMTP id ffacd0b85a97d-381f186fb71mr18732139f8f.29.1731575633401; Thu, 14 Nov 2024 01:13:53 -0800 (PST) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Ved Shanbhogue , Atish Patra , qemu-devel@nongnu.org Subject: [PATCH v5 9/9] target/riscv: Add Smdbltrp ISA extension enable switch Date: Thu, 14 Nov 2024 10:13:30 +0100 Message-ID: <20241114091332.108811-10-cleger@rivosinc.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114091332.108811-1-cleger@rivosinc.com> References: <20241114091332.108811-1-cleger@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=cleger@rivosinc.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1731575736525116600 Add the switch to enable the Smdbltrp ISA extension. Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 15b21e4f7d..1323effdae 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -183,6 +183,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), + ISA_EXT_DATA_ENTRY(smdbltrp, PRIV_VERSION_1_13_0, ext_smdbltrp), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), @@ -1506,6 +1507,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true), =20 MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false), + MULTI_EXT_CFG_BOOL("smdbltrp", ext_smdbltrp, false), MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), MULTI_EXT_CFG_BOOL("smrnmi", ext_smrnmi, false), MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), --=20 2.45.2