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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2ea06f1b17asm485528a91.15.2024.11.13.22.56.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Nov 2024 22:56:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1731567385; x=1732172185; darn=nongnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=joTCuEkN28Wat4wyLgXlDZjsAVW0LdkDoKc0u2sKf/o=; b=GLGFb0XXxFdesgHUEHgO7Rui/brTZr/M2cVS5vCcu2wvdhk2e75w05E0zMvWtpK8GB DrTbSkTEGXlefqwlVcZ/IeSLZ9Uo0QMzmWlhW99jjcSz0Mgtplp9LeQXZ4r9l8kZ32Ls c/TmUPLjYXF5VL+x05NQa2ptlMllmyjhN9iVKn231YMer9jjc/pWTh2yh6BJOmWvDfKD lhXkpXJ3Y2gCXnYWvWNcPkB7EqgX0Itr0d7QnDpnyM2yb4+dXY5fptz5u8HWp0fZ/Vbm GiZWSyobkx3/HoGBa1Go+hkXhWlh1tqwadmsPC4aU7aKytDn/onnU1KEnBQL2kr22NgO pW4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731567385; x=1732172185; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=joTCuEkN28Wat4wyLgXlDZjsAVW0LdkDoKc0u2sKf/o=; b=CCUmB2SZA11VqJHHjd4FKCMzZfe8/Pxq0MrUJkRa0r1kHzkcsQuZxALJPg7dBHegP5 sM2JP+6W3P+eRezFgHUqlZh6jDNV7bu3AbEatWkT/GuQxWC55qw9IY4gmqmUSZh0al1y Aq9hNj7dxQtBMHNTXpSw3jx4RnEtIoL8n1stWzFciDpyoerC9y0hGLhKy7HhzIGR2VuK 7E1VVLp8IyojVLLSPtCPuT1Kr2v1lBI/9rL76lX/dOHfD160wjGcP3t0N97C7vcFw5+B /affEFgsedHsqU+ghCrNKcj9xXnqpK600JhqG+QfrjYr7F3GS5qlC3TWCxBf9MhAgnxK kfzA== X-Gm-Message-State: AOJu0Yyy+bedLoZmWooy+xVin8EOay/UNasW2BzHysxFz9WEpPCAi9nV x81axZut4XGW0Rvbd3ZKQtzukWvIpZq0GAIzJtid0Zp+IfvDcGAA7NfNOxO/iRXSzxvUsaWoTk3 lWDW2aHWMQH6KJV4oboIHIjoTNnp4HLjdxy5JeUr8mDg3GhhGhPkekUixZtd3kIY5BHtFZToFIh omjyAvTsyyIU0duSnuoUpOxctGI0uRcPBRM6o/kR/Jtw4E X-Google-Smtp-Source: AGHT+IHxsYQkSxnHJhC30/V4Ct6WgSOITWNV8vkkJ/ZYF2yCfWEU0rn5EhgkxhwdvVZ2+lsG/NV8WQ== X-Received: by 2002:a05:6a20:2448:b0:1dc:792f:d27c with SMTP id adf61e73a8af0-1dc792fd539mr5263562637.42.1731567385271; Wed, 13 Nov 2024 22:56:25 -0800 (PST) From: Jason Chien To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Jason Chien Subject: [PATCH v2] hw/riscv/riscv-iommu.c: Correct the validness check of iova Date: Thu, 14 Nov 2024 14:56:17 +0800 Message-ID: <20241114065617.25133-1-jason.chien@sifive.com> X-Mailer: git-send-email 2.43.2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=jason.chien@sifive.com; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1731567443629116600 Content-Type: text/plain; charset="utf-8" From RISCV IOMMU spec section 2.1.3: When SXL is 1, the following rules apply: - If the first-stage is not Bare, then a page fault corresponding to the original access type occurs if the IOVA has bits beyond bit 31 set to 1. - If the second-stage is not Bare, then a guest page fault corresponding to the original access type occurs if the incoming GPA has bits beyond bit 33 set to 1. From RISCV IOMMU spec section 2.3 step 17: Use the process specified in Section "Two-Stage Address Translation" of the RISC-V Privileged specification to determine the GPA accessed by the transaction. From RISCV IOMMU spec section 2.3 step 19: Use the second-stage address translation process specified in Section "Two-Stage Address Translation" of the RISC-V Privileged specification to translate the GPA A to determine the SPA accessed by the transaction. This commit adds the iova check with the following rules: - For Sv32, Sv32x4, Sv39x4, Sv48x4 and Sv57x4, the iova must be zero extended. - For Sv39, Sv48 and Sv57, the iova must be signed extended with most significant bit. Signed-off-by: Jason Chien Reviewed-by: Daniel Henrique Barboza --- hw/riscv/riscv-iommu.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index bbc95425b3..ff9deefe37 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -392,9 +392,26 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, R= ISCVIOMMUContext *ctx, =20 /* Address range check before first level lookup */ if (!sc[pass].step) { - const uint64_t va_mask =3D (1ULL << (va_skip + va_bits)) - 1; - if ((addr & va_mask) !=3D addr) { - return RISCV_IOMMU_FQ_CAUSE_DMA_DISABLED; + const uint64_t va_len =3D va_skip + va_bits; + const uint64_t va_mask =3D (1ULL << va_len) - 1; + + if (pass =3D=3D S_STAGE && va_len > 32) { + target_ulong mask, masked_msbs; + + mask =3D (1L << (TARGET_LONG_BITS - (va_len - 1))) - 1; + masked_msbs =3D (addr >> (va_len - 1)) & mask; + + if (masked_msbs !=3D 0 && masked_msbs !=3D mask) { + return (iotlb->perm & IOMMU_WO) ? + RISCV_IOMMU_FQ_CAUSE_WR_FAULT_S : + RISCV_IOMMU_FQ_CAUSE_RD_FAULT_S; + } + } else { + if ((addr & va_mask) !=3D addr) { + return (iotlb->perm & IOMMU_WO) ? + RISCV_IOMMU_FQ_CAUSE_WR_FAULT_VS : + RISCV_IOMMU_FQ_CAUSE_RD_FAULT_VS; + } } } =20 --=20 2.43.2