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Wed, 13 Nov 2024 17:15:55 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 20/24] exec: Declare tlb_vaddr_to_host() in 'exec/cputlb.h' Date: Thu, 14 Nov 2024 02:13:05 +0100 Message-ID: <20241114011310.3615-21-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731547051776116600 Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/exec/cpu_ldst.h | 25 ------------------------- include/exec/cputlb.h | 26 ++++++++++++++++++++++++++ target/arm/tcg/helper-a64.c | 1 + target/ppc/mem_helper.c | 1 + 4 files changed, 28 insertions(+), 25 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 769e9fc440..eec47ca05e 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -69,7 +69,6 @@ #include "exec/memopidx.h" #include "exec/vaddr.h" #include "exec/abi_ptr.h" -#include "exec/mmu-access-type.h" #include "qemu/int128.h" =20 #if defined(CONFIG_USER_ONLY) @@ -311,30 +310,6 @@ uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr= ); uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr); uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr); =20 -/** - * tlb_vaddr_to_host: - * @env: CPUArchState - * @addr: guest virtual address to look up - * @access_type: 0 for read, 1 for write, 2 for execute - * @mmu_idx: MMU index to use for lookup - * - * Look up the specified guest virtual index in the TCG softmmu TLB. - * If we can translate a host virtual address suitable for direct RAM - * access, without causing a guest exception, then return it. - * Otherwise (TLB entry is for an I/O access, guest software - * TLB fill required, etc) return NULL. - */ -#ifdef CONFIG_USER_ONLY -static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, - MMUAccessType access_type, int mmu_i= dx) -{ - return g2h(env_cpu(env), addr); -} -#else -void *tlb_vaddr_to_host(CPUArchState *env, vaddr addr, - MMUAccessType access_type, int mmu_idx); -#endif - /* * For user-only, helpers that use guest to host address translation * must protect the actual host memory access by recording 'retaddr' diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 07c4bc669e..4acc2c6235 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -20,6 +20,7 @@ #ifndef CPUTLB_H #define CPUTLB_H =20 +#include "exec/abi_ptr.h" #include "exec/cpu-common.h" #include "exec/hwaddr.h" #include "exec/memattrs.h" @@ -306,4 +307,29 @@ void tlb_set_page(CPUState *cpu, vaddr addr, hwaddr paddr, int prot, int mmu_idx, vaddr size); =20 +/** + * tlb_vaddr_to_host: + * @env: CPUArchState + * @addr: guest virtual address to look up + * @access_type: 0 for read, 1 for write, 2 for execute + * @mmu_idx: MMU index to use for lookup + * + * Look up the specified guest virtual index in the TCG softmmu TLB. + * If we can translate a host virtual address suitable for direct RAM + * access, without causing a guest exception, then return it. + * Otherwise (TLB entry is for an I/O access, guest software + * TLB fill required, etc) return NULL. + */ +#ifdef CONFIG_USER_ONLY +#include "user/guest-host.h" +static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, + MMUAccessType access_type, int mmu_i= dx) +{ + return g2h(env_cpu(env), addr); +} +#else +void *tlb_vaddr_to_host(CPUArchState *env, vaddr addr, + MMUAccessType access_type, int mmu_idx); +#endif + #endif diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 8f42a28d07..9cb5d8ee53 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -30,6 +30,7 @@ #include "qemu/crc32c.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "exec/cputlb.h" #include "qemu/int128.h" #include "qemu/atomic128.h" #include "fpu/softfloat.h" diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 51b137febd..44974b25f8 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -24,6 +24,7 @@ #include "exec/helper-proto.h" #include "helper_regs.h" #include "exec/cpu_ldst.h" +#include "exec/cputlb.h" #include "internal.h" #include "qemu/atomic128.h" =20 --=20 2.45.2