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Wed, 13 Nov 2024 17:15:31 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 17/24] exec: Declare tlb_set_page() in 'exec/cputlb.h' Date: Thu, 14 Nov 2024 02:13:02 +0100 Message-ID: <20241114011310.3615-18-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731547127975116600 Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/exec/cputlb.h | 11 +++++++++++ include/exec/exec-all.h | 9 --------- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index ae4798a017..9075d94ec5 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -108,4 +108,15 @@ void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, hwaddr paddr, MemTxAttrs attrs, int prot, int mmu_idx, vaddr size); =20 +/** + * tlb_set_page: + * + * This function is equivalent to calling tlb_set_page_with_attrs() + * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided + * as a convenience for CPUs which don't use memory transaction attributes. + */ +void tlb_set_page(CPUState *cpu, vaddr addr, + hwaddr paddr, int prot, + int mmu_idx, vaddr size); + #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 2b314d658b..2e58540005 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -174,15 +174,6 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUStat= e *cpu, uint16_t idxmap, unsigned bits); =20 -/* tlb_set_page: - * - * This function is equivalent to calling tlb_set_page_with_attrs() - * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided - * as a convenience for CPUs which don't use memory transaction attributes. - */ -void tlb_set_page(CPUState *cpu, vaddr addr, - hwaddr paddr, int prot, - int mmu_idx, vaddr size); #else static inline void tlb_flush_page(CPUState *cpu, vaddr addr) { --=20 2.45.2