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Wed, 13 Nov 2024 17:13:37 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 01/24] exec/cpu-all: Include missing 'exec/cpu-defs.h' header Date: Thu, 14 Nov 2024 02:12:46 +0100 Message-ID: <20241114011310.3615-2-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731546885367116600 TARGET_PAGE_BITS is defined in "exec/cpu-defs.h". Include it in order to avoid when refactoring: In file included from ../../system/watchpoint.c:23: include/exec/cpu-all.h:356:19: error: use of undeclared identifier 'TARGE= T_PAGE_BITS' 356 | QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); | ^ Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- include/exec/cpu-all.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 45e6676938..1c40e27672 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -136,7 +136,7 @@ static inline void stl_phys_notdirty(AddressSpace *as, = hwaddr addr, uint32_t val #endif =20 /* page related stuff */ - +#include "exec/cpu-defs.h" #ifdef TARGET_PAGE_BITS_VARY # include "exec/page-vary.h" extern const TargetPageBits target_page; --=20 2.45.2 From nobody Sat Nov 23 17:19:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731546921392116600 "exec/cpu-defs.h" should be kept as minimal as possible; besides these includes don't seem necessay. Remove them. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson Tested-by: Thomas Huth --- include/exec/cpu-defs.h | 8 -------- 1 file changed, 8 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 0dbef3010c..ae18398fa9 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -23,14 +23,6 @@ #error cpu.h included from common code #endif =20 -#include "qemu/host-utils.h" -#include "qemu/thread.h" -#ifndef CONFIG_USER_ONLY -#include "exec/hwaddr.h" -#endif -#include "exec/memattrs.h" -#include "hw/core/cpu.h" - #include "cpu-param.h" =20 #ifndef TARGET_LONG_BITS --=20 2.45.2 From nobody Sat Nov 23 17:19:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Include it in order to avoid when refactoring: include/exec/translation-block.h:56:5: error: unknown type name 'vaddr' 56 | vaddr pc; | ^ Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- include/exec/translation-block.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/translation-block.h b/include/exec/translation-bl= ock.h index a6d1af6e9b..b99afb0077 100644 --- a/include/exec/translation-block.h +++ b/include/exec/translation-block.h @@ -9,6 +9,7 @@ =20 #include "qemu/thread.h" #include "exec/cpu-common.h" +#include "exec/vaddr.h" #ifdef CONFIG_USER_ONLY #include "qemu/interval-tree.h" #endif --=20 2.45.2 From nobody Sat Nov 23 17:19:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731547196268116600 TB compile flags are defined in "exec/translation-block.h". Include it in order to avoid when refactoring: accel/tcg/tcg-accel-ops.c:62:36: error: use of undeclared identifier 'CF_= CLUSTER_SHIFT' 62 | cflags =3D cpu->cluster_index << CF_CLUSTER_SHIFT; | ^ accel/tcg/tcg-accel-ops.c:64:26: error: use of undeclared identifier 'CF_= PARALLEL' 64 | cflags |=3D parallel ? CF_PARALLEL : 0; | ^ accel/tcg/tcg-accel-ops.c:65:34: error: use of undeclared identifier 'CF_= USE_ICOUNT' 65 | cflags |=3D icount_enabled() ? CF_USE_ICOUNT : 0; | ^ Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- accel/tcg/tcg-accel-ops.c | 1 + 1 file changed, 1 insertion(+) diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 3c19e68a79..22486c5dff 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -35,6 +35,7 @@ #include "exec/exec-all.h" #include "exec/hwaddr.h" #include "exec/tb-flush.h" +#include "exec/translation-block.h" #include "gdbstub/enums.h" =20 #include "hw/core/cpu.h" --=20 2.45.2 From nobody Sat Nov 23 17:19:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1731547078; cv=none; d=zohomail.com; s=zohoarc; b=XyVKzZOMvpsNPLEYWYCMDzFAkcsDHz4imH4eOXtybx49+Olhv5XAH0z+91/h8okWusaQ8fBiOfI3fr3PqovkO8p2645iKNKLrPytJ5LOhgQcZp8IUUVCsLiebZF8rxXigQ6g2lhKnbzRN1dZtYwxlKwWkvmIVGNg5gb/vK1qUx4= ARC-Message-Signature: i=1; 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AJvYcCVnjvzZA+uZiebdIBhkKdvG86Z+aCghZJv0QqIDzdIcQbNYgC8Oef4iUBVsdhV/v0WltTrtQwyJKmXk@nongnu.org X-Gm-Message-State: AOJu0YzYtvZsRVIxBx1ZG9B+FMj36mr/KIPOrk4xeBdTefPh8rd9swuR xXxieuBY//N9x6KDPhX3DSEnz6TJOKU7u3GyCpkwzIy4C46JKPiBWWkX+YcdLKM= X-Google-Smtp-Source: AGHT+IEn2so/ixH18AvrpdZMy3nJh7glbi+y5QwToKvNKI1CwZqSHbNiU7EXqtTNTTpXjuGdZdx7cQ== X-Received: by 2002:a5d:648b:0:b0:37d:47ee:10d9 with SMTP id ffacd0b85a97d-381f1873485mr19654057f8f.34.1731546844586; Wed, 13 Nov 2024 17:14:04 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 05/24] target/i386/helper: Include missing 'exec/translation-block.h' header Date: Thu, 14 Nov 2024 02:12:50 +0100 Message-ID: <20241114011310.3615-6-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731547079847116600 TB compile flags are defined in "exec/translation-block.h". Include it in order to avoid when refactoring: target/i386/helper.c:536:28: error: use of undeclared identifier 'CF_PCRE= L' 536 | if (tcg_cflags_has(cs, CF_PCREL)) { | ^ Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- target/i386/helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/helper.c b/target/i386/helper.c index 01a268a30b..75c52e2143 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -21,6 +21,7 @@ #include "qapi/qapi-events-run-state.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/translation-block.h" #include "sysemu/runstate.h" #ifndef CONFIG_USER_ONLY #include "sysemu/hw_accel.h" --=20 2.45.2 From nobody Sat Nov 23 17:19:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731546983500116600 The TranslationBlock structure is declared in "exec/translation-block.h", along with the TB compile flag definitions. Include the header in order to avoid when refactoring: target/rx/cpu.c:50:42: error: use of undeclared identifier 'CF_PCREL' 50 | tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); | ^ target/rx/cpu.c:51:21: error: incomplete definition of type 'struct Trans= lationBlock' 51 | cpu->env.pc =3D tb->pc; | ~~^ include/qemu/typedefs.h:116:16: note: forward declaration of 'struct Tran= slationBlock' 116 | typedef struct TranslationBlock TranslationBlock; | ^ Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- target/rx/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 65a74ce720..945ae6e9e5 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -23,6 +23,7 @@ #include "migration/vmstate.h" #include "exec/exec-all.h" #include "exec/page-protection.h" +#include "exec/translation-block.h" #include "hw/loader.h" #include "fpu/softfloat.h" #include "tcg/debug-assert.h" --=20 2.45.2 From nobody Sat Nov 23 17:19:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 13 Nov 2024 17:14:19 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 07/24] system/watchpoint: Include missing 'exec/cpu-all.h' header Date: Thu, 14 Nov 2024 02:12:52 +0100 Message-ID: <20241114011310.3615-8-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731546967498116600 TARGET_PAGE_MASK is defined in "exec/cpu-all.h". Include it in order to avoid when refactoring: system/watchpoint.c:52:24: error: use of undeclared identifier 'TARGET_PA= GE_MASK' 52 | in_page =3D -(addr | TARGET_PAGE_MASK); | ^ Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- system/watchpoint.c | 1 + 1 file changed, 1 insertion(+) diff --git a/system/watchpoint.c b/system/watchpoint.c index 2aa2a9ea63..f7366574a3 100644 --- a/system/watchpoint.c +++ b/system/watchpoint.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" #include "exec/exec-all.h" +#include "exec/cpu-all.h" #include "hw/core/cpu.h" =20 /* Add a watchpoint. */ --=20 2.45.2 From nobody Sat Nov 23 17:19:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731547101868116600 abi_long type is defined in "user/abitypes.h". Include it in order to avoid when refactoring: linux-user/aarch64/mte_user_helper.h:30:42: error: unknown type name =E2= =80=98abi_long=E2=80=99; did you mean =E2=80=98u_long=E2=80=99? 30 | void arm_set_mte_tcf0(CPUArchState *env, abi_long value); | ^~~~~~~~ | u_long Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- linux-user/aarch64/mte_user_helper.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/linux-user/aarch64/mte_user_helper.h b/linux-user/aarch64/mte_= user_helper.h index 8685e5175a..0c53abda22 100644 --- a/linux-user/aarch64/mte_user_helper.h +++ b/linux-user/aarch64/mte_user_helper.h @@ -9,6 +9,8 @@ #ifndef AARCH64_MTE_USER_HELPER_H #define AARCH64_MTE USER_HELPER_H =20 +#include "user/abitypes.h" + #ifndef PR_MTE_TCF_SHIFT # define PR_MTE_TCF_SHIFT 1 # define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT) --=20 2.45.2 From nobody Sat Nov 23 17:19:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731547057705116600 "exec/ram_addr.h" contains system specific declarations. Restrict its inclusion to sysemu to avoid build errors when refactoring. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- target/arm/tcg/mte_helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 9d2ba287ee..b017b26d07 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -23,7 +23,9 @@ #include "internals.h" #include "exec/exec-all.h" #include "exec/page-protection.h" +#ifndef CONFIG_USER_ONLY #include "exec/ram_addr.h" +#endif #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "hw/core/tcg-cpu-ops.h" --=20 2.45.2 From nobody Sat Nov 23 17:19:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1731547159; cv=none; d=zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731547160046116600 Move the #endif guard where it belongs to restrict the cpu_untagged_addr() implementation to user emulation. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- target/arm/cpu.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d86e641280..12b8466542 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3355,8 +3355,8 @@ extern const uint64_t pred_esz_masks[5]; #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) =20 #ifdef CONFIG_USER_ONLY + #define TARGET_PAGE_DATA_SIZE (TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1)) -#endif =20 #ifdef TARGET_TAGGED_ADDRESSES /** @@ -3382,6 +3382,7 @@ static inline target_ulong cpu_untagged_addr(CPUState= *cs, target_ulong x) } return x; } -#endif +#endif /* TARGET_TAGGED_ADDRESSES */ +#endif /* CONFIG_USER_ONLY */ =20 #endif --=20 2.45.2 From nobody Sat Nov 23 17:19:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- include/exec/cpu-all.h | 34 +-------------- include/exec/cpu_ldst.h | 47 +-------------------- include/user/guest-host.h | 87 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 89 insertions(+), 79 deletions(-) create mode 100644 include/user/guest-host.h diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 1c40e27672..1c8e0446d0 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -64,39 +64,7 @@ =20 /* MMU memory access macros */ =20 -#if defined(CONFIG_USER_ONLY) -#include "user/abitypes.h" - -/* - * If non-zero, the guest virtual address space is a contiguous subset - * of the host virtual address space, i.e. '-R reserved_va' is in effect - * either from the command-line or by default. The value is the last - * byte of the guest address space e.g. UINT32_MAX. - * - * If zero, the host and guest virtual address spaces are intermingled. - */ -extern unsigned long reserved_va; - -/* - * Limit the guest addresses as best we can. - * - * When not using -R reserved_va, we cannot really limit the guest - * to less address space than the host. For 32-bit guests, this - * acts as a sanity check that we're not giving the guest an address - * that it cannot even represent. For 64-bit guests... the address - * might not be what the real kernel would give, but it is at least - * representable in the guest. - * - * TODO: Improve address allocation to avoid this problem, and to - * avoid setting bits at the top of guest addresses that might need - * to be used for tags. - */ -#define GUEST_ADDR_MAX_ \ - ((MIN_CONST(TARGET_VIRT_ADDR_SPACE_BITS, TARGET_ABI_BITS) <=3D 32) ? \ - UINT32_MAX : ~0ul) -#define GUEST_ADDR_MAX (reserved_va ? : GUEST_ADDR_MAX_) - -#else +#if !defined(CONFIG_USER_ONLY) =20 #include "exec/hwaddr.h" =20 diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index dac12bd8eb..a26ab49b0b 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -72,52 +72,7 @@ #include "qemu/int128.h" =20 #if defined(CONFIG_USER_ONLY) - -#include "user/guest-base.h" - -#ifndef TARGET_TAGGED_ADDRESSES -static inline abi_ptr cpu_untagged_addr(CPUState *cs, abi_ptr x) -{ - return x; -} -#endif - -/* All direct uses of g2h and h2g need to go away for usermode softmmu. */ -static inline void *g2h_untagged(abi_ptr x) -{ - return (void *)((uintptr_t)(x) + guest_base); -} - -static inline void *g2h(CPUState *cs, abi_ptr x) -{ - return g2h_untagged(cpu_untagged_addr(cs, x)); -} - -static inline bool guest_addr_valid_untagged(abi_ulong x) -{ - return x <=3D GUEST_ADDR_MAX; -} - -static inline bool guest_range_valid_untagged(abi_ulong start, abi_ulong l= en) -{ - return len - 1 <=3D GUEST_ADDR_MAX && start <=3D GUEST_ADDR_MAX - len = + 1; -} - -#define h2g_valid(x) \ - (HOST_LONG_BITS <=3D TARGET_VIRT_ADDR_SPACE_BITS || \ - (uintptr_t)(x) - guest_base <=3D GUEST_ADDR_MAX) - -#define h2g_nocheck(x) ({ \ - uintptr_t __ret =3D (uintptr_t)(x) - guest_base; \ - (abi_ptr)__ret; \ -}) - -#define h2g(x) ({ \ - /* Check if given address fits target address space */ \ - assert(h2g_valid(x)); \ - h2g_nocheck(x); \ -}) - +#include "user/guest-host.h" #endif /* CONFIG_USER_ONLY */ =20 uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr); diff --git a/include/user/guest-host.h b/include/user/guest-host.h new file mode 100644 index 0000000000..8d2079bbbb --- /dev/null +++ b/include/user/guest-host.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: LGPL-2.1-or-later */ +/* + * guest <-> host helpers. + * + * Copyright (c) 2003 Fabrice Bellard + */ + +#ifndef USER_GUEST_HOST_H +#define USER_GUEST_HOST_H + +#include "user/abitypes.h" +#include "user/guest-base.h" +#include "cpu.h" + +/* + * If non-zero, the guest virtual address space is a contiguous subset + * of the host virtual address space, i.e. '-R reserved_va' is in effect + * either from the command-line or by default. The value is the last + * byte of the guest address space e.g. UINT32_MAX. + * + * If zero, the host and guest virtual address spaces are intermingled. + */ +extern unsigned long reserved_va; + +/* + * Limit the guest addresses as best we can. + * + * When not using -R reserved_va, we cannot really limit the guest + * to less address space than the host. For 32-bit guests, this + * acts as a sanity check that we're not giving the guest an address + * that it cannot even represent. For 64-bit guests... the address + * might not be what the real kernel would give, but it is at least + * representable in the guest. + * + * TODO: Improve address allocation to avoid this problem, and to + * avoid setting bits at the top of guest addresses that might need + * to be used for tags. + */ +#define GUEST_ADDR_MAX_ \ + ((MIN_CONST(TARGET_VIRT_ADDR_SPACE_BITS, TARGET_ABI_BITS) <=3D 32) ? \ + UINT32_MAX : ~0ul) +#define GUEST_ADDR_MAX (reserved_va ? : GUEST_ADDR_MAX_) + +#ifndef TARGET_TAGGED_ADDRESSES +static inline abi_ptr cpu_untagged_addr(CPUState *cs, abi_ptr x) +{ + return x; +} +#endif + +/* All direct uses of g2h and h2g need to go away for usermode softmmu. */ +static inline void *g2h_untagged(abi_ptr x) +{ + return (void *)((uintptr_t)(x) + guest_base); +} + +static inline void *g2h(CPUState *cs, abi_ptr x) +{ + return g2h_untagged(cpu_untagged_addr(cs, x)); +} + +static inline bool guest_addr_valid_untagged(abi_ulong x) +{ + return x <=3D GUEST_ADDR_MAX; +} + +static inline bool guest_range_valid_untagged(abi_ulong start, abi_ulong l= en) +{ + return len - 1 <=3D GUEST_ADDR_MAX && start <=3D GUEST_ADDR_MAX - len = + 1; +} + +#define h2g_valid(x) \ + (HOST_LONG_BITS <=3D TARGET_VIRT_ADDR_SPACE_BITS || \ + (uintptr_t)(x) - guest_base <=3D GUEST_ADDR_MAX) + +#define h2g_nocheck(x) ({ \ + uintptr_t __ret =3D (uintptr_t)(x) - guest_base; \ + (abi_ptr)__ret; \ +}) + +#define h2g(x) ({ \ + /* Check if given address fits target address space */ \ + assert(h2g_valid(x)); \ + h2g_nocheck(x); \ +}) + +#endif --=20 2.45.2 From nobody Sat Nov 23 17:19:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1731547099; cv=none; d=zohomail.com; s=zohoarc; b=QPbq45eIfsD0mv/nZ6RbAt7JG+LdgToYLiwubbXAQGNMwW4jpxEhqJypzV7CM3YmzVhEKWBEZLElM69VypymtfrNNQrpKivNO5/2nE19xGf4i9gyCDGcGEB7bHQAhI8ZXOdtFd5129UWo5SvggZdm4FW4UJJkCoigMdSECUgzTs= ARC-Message-Signature: i=1; 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AJvYcCW/1r32Hzwq48DY5WVepq06CvP1vZSpgn4nqMZRlFVyJ+dg8x/Es0kW+desdSVcQfJgUVxZAkiv9g/F@nongnu.org X-Gm-Message-State: AOJu0YzRrT3cDNbIGf58ebbzAEiy/4eXJly6ytjFHyQEoW5cDL93IFpg gXYVtyZXO++kuOVfwHrM6uLg97lInpkEZgLaZea/MqwA85tKT+te3rWj3tvQebY= X-Google-Smtp-Source: AGHT+IGRRIBLDqHxwGvygVd7DolZQGg3AA35b02RB8xxCyDjdgNLnjdc3+2vgRQgLmodm+ip4IylVg== X-Received: by 2002:a05:6000:18a3:b0:381:f443:21bf with SMTP id ffacd0b85a97d-3820df5bcafmr3699799f8f.2.1731546895166; Wed, 13 Nov 2024 17:14:55 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 12/24] accel/tcg: Have tlb_vaddr_to_host() use vaddr type Date: Thu, 14 Nov 2024 02:12:57 +0100 Message-ID: <20241114011310.3615-13-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731547099848116600 abi_ptr is expected to be used in user emulation. tlb_vaddr_to_host() uses it, but can be used in system emulation. Replace the type by 'vaddr' which is equivalent on user emulation but also works on system. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- include/exec/cpu_ldst.h | 3 ++- accel/tcg/cputlb.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index a26ab49b0b..769e9fc440 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -67,6 +67,7 @@ #endif =20 #include "exec/memopidx.h" +#include "exec/vaddr.h" #include "exec/abi_ptr.h" #include "exec/mmu-access-type.h" #include "qemu/int128.h" @@ -330,7 +331,7 @@ static inline void *tlb_vaddr_to_host(CPUArchState *env= , abi_ptr addr, return g2h(env_cpu(env), addr); } #else -void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, +void *tlb_vaddr_to_host(CPUArchState *env, vaddr addr, MMUAccessType access_type, int mmu_idx); #endif =20 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index b76a4eac4e..080cbcb34d 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1504,7 +1504,7 @@ void *probe_access(CPUArchState *env, vaddr addr, int= size, return host; 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Wed, 13 Nov 2024 17:15:02 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 13/24] exec: Declare tlb_reset_dirty*() in 'exec/cputlb.h' Date: Thu, 14 Nov 2024 02:12:58 +0100 Message-ID: <20241114011310.3615-14-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/exec/cputlb.h | 7 +++++++ include/exec/exec-all.h | 3 --- include/exec/ram_addr.h | 1 + system/physmem.c | 1 + 4 files changed, 9 insertions(+), 3 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index ef18642a32..6cac7d530f 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -32,4 +32,11 @@ void tlb_unprotect_code(ram_addr_t ram_addr); =20 #endif /* CONFIG_TCG */ =20 +#ifndef CONFIG_USER_ONLY + +void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); +void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length); + +#endif + #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 2e4c4cc4b4..2c06e54387 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -589,9 +589,6 @@ static inline void mmap_lock(void) {} static inline void mmap_unlock(void) {} #define WITH_MMAP_LOCK_GUARD() =20 -void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); -void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length); - MemoryRegionSection * address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, hwaddr *xlat, hwaddr *plen, diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index 891c44cf2d..b6d5551549 100644 --- a/include/exec/ram_addr.h +++ b/include/exec/ram_addr.h @@ -23,6 +23,7 @@ #include "cpu.h" #include "sysemu/xen.h" #include "sysemu/tcg.h" +#include "exec/cputlb.h" #include "exec/ramlist.h" #include "exec/ramblock.h" #include "exec/exec-all.h" diff --git a/system/physmem.c b/system/physmem.c index dc1db3a384..3f937a5e58 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -32,6 +32,7 @@ #endif /* CONFIG_TCG */ =20 #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/target_page.h" #include "hw/qdev-core.h" --=20 2.45.2 From nobody Sat Nov 23 17:19:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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Wed, 13 Nov 2024 17:15:08 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 14/24] exec: Declare tlb_init/destroy() in 'exec/cputlb.h' Date: Thu, 14 Nov 2024 02:12:59 +0100 Message-ID: <20241114011310.3615-15-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731546985701116600 Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/exec/cputlb.h | 28 +++++++++++++++++++++++----- include/exec/exec-all.h | 17 ----------------- accel/tcg/cpu-exec.c | 1 + 3 files changed, 24 insertions(+), 22 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 6cac7d530f..5386e53806 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -22,15 +22,33 @@ =20 #include "exec/cpu-common.h" =20 -#ifdef CONFIG_TCG +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) + +/** + * tlb_init - initialize a CPU's TLB + * @cpu: CPU whose TLB should be initialized + */ +void tlb_init(CPUState *cpu); + +/** + * tlb_destroy - destroy a CPU's TLB + * @cpu: CPU whose TLB should be destroyed + */ +void tlb_destroy(CPUState *cpu); =20 -#if !defined(CONFIG_USER_ONLY) -/* cputlb.c */ void tlb_protect_code(ram_addr_t ram_addr); void tlb_unprotect_code(ram_addr_t ram_addr); -#endif =20 -#endif /* CONFIG_TCG */ +#else + +static inline void tlb_init(CPUState *cpu) +{ +} +static inline void tlb_destroy(CPUState *cpu) +{ +} + +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ =20 #ifndef CONFIG_USER_ONLY =20 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 2c06e54387..d792203773 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -47,17 +47,6 @@ static inline bool cpu_loop_exit_requested(CPUState *cpu) } =20 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) -/* cputlb.c */ -/** - * tlb_init - initialize a CPU's TLB - * @cpu: CPU whose TLB should be initialized - */ -void tlb_init(CPUState *cpu); -/** - * tlb_destroy - destroy a CPU's TLB - * @cpu: CPU whose TLB should be destroyed - */ -void tlb_destroy(CPUState *cpu); /** * tlb_flush_page: * @cpu: CPU whose TLB should be flushed @@ -242,12 +231,6 @@ void tlb_set_page(CPUState *cpu, vaddr addr, hwaddr paddr, int prot, int mmu_idx, vaddr size); #else -static inline void tlb_init(CPUState *cpu) -{ -} -static inline void tlb_destroy(CPUState *cpu) -{ -} static inline void tlb_flush_page(CPUState *cpu, vaddr addr) { } diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8163295f34..8770493590 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -24,6 +24,7 @@ #include "hw/core/tcg-cpu-ops.h" #include "trace.h" #include "disas/disas.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "tcg/tcg.h" #include "qemu/atomic.h" --=20 2.45.2 From nobody Sat Nov 23 17:19:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/exec/cputlb.h | 23 +++++++++++++++++++++++ include/exec/exec-all.h | 22 ---------------------- target/sparc/mmu_helper.c | 2 +- 3 files changed, 24 insertions(+), 23 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 5386e53806..f6205d5306 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -21,6 +21,7 @@ #define CPUTLB_H =20 #include "exec/cpu-common.h" +#include "exec/vaddr.h" =20 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) =20 @@ -57,4 +58,26 @@ void tlb_reset_dirty_range_all(ram_addr_t start, ram_add= r_t length); =20 #endif =20 +/** + * tlb_set_page_full: + * @cpu: CPU context + * @mmu_idx: mmu index of the tlb to modify + * @addr: virtual address of the entry to add + * @full: the details of the tlb entry + * + * Add an entry to @cpu tlb index @mmu_idx. All of the fields of + * @full must be filled, except for xlat_section, and constitute + * the complete description of the translated page. + * + * This is generally called by the target tlb_fill function after + * having performed a successful page table walk to find the physical + * address and attributes for the translation. + * + * At most one entry for a given virtual address is permitted. Only a + * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only + * used by tlb_flush_page. + */ +void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, + CPUTLBEntryFull *full); + #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index d792203773..79649537b0 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -174,28 +174,6 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUStat= e *cpu, uint16_t idxmap, unsigned bits); =20 -/** - * tlb_set_page_full: - * @cpu: CPU context - * @mmu_idx: mmu index of the tlb to modify - * @addr: virtual address of the entry to add - * @full: the details of the tlb entry - * - * Add an entry to @cpu tlb index @mmu_idx. All of the fields of - * @full must be filled, except for xlat_section, and constitute - * the complete description of the translated page. - * - * This is generally called by the target tlb_fill function after - * having performed a successful page table walk to find the physical - * address and attributes for the translation. - * - * At most one entry for a given virtual address is permitted. Only a - * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only - * used by tlb_flush_page. - */ -void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, - CPUTLBEntryFull *full); - /** * tlb_set_page_with_attrs: * @cpu: CPU to add this TLB entry for diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 9ff06026b8..7548d01777 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "qemu/qemu-print.h" #include "trace.h" --=20 2.45.2 From nobody Sat Nov 23 17:19:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731547101952116600 Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/exec/cputlb.h | 28 ++++++++++++++++++++++++++++ include/exec/exec-all.h | 25 ------------------------- target/i386/tcg/sysemu/excp_helper.c | 2 +- target/microblaze/helper.c | 2 +- 4 files changed, 30 insertions(+), 27 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index f6205d5306..ae4798a017 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -21,6 +21,8 @@ #define CPUTLB_H =20 #include "exec/cpu-common.h" +#include "exec/hwaddr.h" +#include "exec/memattrs.h" #include "exec/vaddr.h" =20 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) @@ -80,4 +82,30 @@ void tlb_reset_dirty_range_all(ram_addr_t start, ram_add= r_t length); void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr, CPUTLBEntryFull *full); =20 +/** + * tlb_set_page_with_attrs: + * @cpu: CPU to add this TLB entry for + * @addr: virtual address of page to add entry for + * @paddr: physical address of the page + * @attrs: memory transaction attributes + * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) + * @mmu_idx: MMU index to insert TLB entry for + * @size: size of the page in bytes + * + * Add an entry to this CPU's TLB (a mapping from virtual address + * @addr to physical address @paddr) with the specified memory + * transaction attributes. This is generally called by the target CPU + * specific code after it has been called through the tlb_fill() + * entry point and performed a successful page table walk to find + * the physical address and attributes for the virtual address + * which provoked the TLB miss. + * + * At most one entry for a given virtual address is permitted. Only a + * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only + * used by tlb_flush_page. + */ +void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, + hwaddr paddr, MemTxAttrs attrs, + int prot, int mmu_idx, vaddr size); + #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 79649537b0..2b314d658b 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -174,31 +174,6 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUStat= e *cpu, uint16_t idxmap, unsigned bits); =20 -/** - * tlb_set_page_with_attrs: - * @cpu: CPU to add this TLB entry for - * @addr: virtual address of page to add entry for - * @paddr: physical address of the page - * @attrs: memory transaction attributes - * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) - * @mmu_idx: MMU index to insert TLB entry for - * @size: size of the page in bytes - * - * Add an entry to this CPU's TLB (a mapping from virtual address - * @addr to physical address @paddr) with the specified memory - * transaction attributes. This is generally called by the target CPU - * specific code after it has been called through the tlb_fill() - * entry point and performed a successful page table walk to find - * the physical address and attributes for the virtual address - * which provoked the TLB miss. - * - * At most one entry for a given virtual address is permitted. Only a - * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only - * used by tlb_flush_page. - */ -void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, - hwaddr paddr, MemTxAttrs attrs, - int prot, int mmu_idx, vaddr size); /* tlb_set_page: * * This function is equivalent to calling tlb_set_page_with_attrs() diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index da187c8792..cda0152b80 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/cpu_ldst.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "tcg/helper-tcg.h" =20 diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 5d3259ce31..27fc929bee 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -20,7 +20,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "qemu/host-utils.h" #include "exec/log.h" --=20 2.45.2 From nobody Sat Nov 23 17:19:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 13 Nov 2024 17:15:31 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 17/24] exec: Declare tlb_set_page() in 'exec/cputlb.h' Date: Thu, 14 Nov 2024 02:13:02 +0100 Message-ID: <20241114011310.3615-18-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/exec/cputlb.h | 11 +++++++++++ include/exec/exec-all.h | 9 --------- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index ae4798a017..9075d94ec5 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -108,4 +108,15 @@ void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, hwaddr paddr, MemTxAttrs attrs, int prot, int mmu_idx, vaddr size); =20 +/** + * tlb_set_page: + * + * This function is equivalent to calling tlb_set_page_with_attrs() + * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided + * as a convenience for CPUs which don't use memory transaction attributes. + */ +void tlb_set_page(CPUState *cpu, vaddr addr, + hwaddr paddr, int prot, + int mmu_idx, vaddr size); + #endif diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 2b314d658b..2e58540005 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -174,15 +174,6 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUStat= e *cpu, uint16_t idxmap, unsigned bits); =20 -/* tlb_set_page: - * - * This function is equivalent to calling tlb_set_page_with_attrs() - * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided - * as a convenience for CPUs which don't use memory transaction attributes. - */ -void tlb_set_page(CPUState *cpu, vaddr addr, - hwaddr paddr, int prot, - int mmu_idx, vaddr size); #else static inline void tlb_flush_page(CPUState *cpu, vaddr addr) { --=20 2.45.2 From nobody Sat Nov 23 17:19:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1731547212; cv=none; d=zohomail.com; s=zohoarc; b=kPvmNNI23WZKIfvkA6BlVucgKMk8fLGhNyHksDgGp5iWmnERrJhB43eGCP78ESQcKCC3qO4m9jS1YPof7xUtEQuGJJ72UIPa21coyymwonluN0YaTH7cwjWBQZatvk+agxIwCjg0CygRQ7irJw1No5PxpZBIXwaDY/mxmxmgTbg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1731547212; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Wed, 13 Nov 2024 17:15:39 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 18/24] exec: Declare tlb_flush*() in 'exec/cputlb.h' Date: Thu, 14 Nov 2024 02:13:03 +0100 Message-ID: <20241114011310.3615-19-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731547214429116600 Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- include/exec/cputlb.h | 187 +++++++++++++++++++++++++++ include/exec/exec-all.h | 183 -------------------------- accel/tcg/tcg-accel-ops.c | 1 + cpu-target.c | 1 + hw/intc/armv7m_nvic.c | 2 +- hw/ppc/spapr_nested.c | 1 + hw/sh4/sh7750.c | 1 + system/watchpoint.c | 2 +- target/alpha/helper.c | 2 +- target/alpha/sys_helper.c | 2 +- target/arm/helper.c | 1 + target/avr/helper.c | 2 +- target/hppa/mem_helper.c | 1 + target/i386/helper.c | 1 + target/i386/machine.c | 2 +- target/i386/tcg/fpu_helper.c | 2 +- target/i386/tcg/misc_helper.c | 2 +- target/i386/tcg/sysemu/misc_helper.c | 2 +- target/i386/tcg/sysemu/svm_helper.c | 2 +- target/loongarch/tcg/csr_helper.c | 2 +- target/loongarch/tcg/tlb_helper.c | 2 +- target/m68k/helper.c | 2 +- target/microblaze/mmu.c | 2 +- target/mips/sysemu/cp0.c | 2 +- target/mips/tcg/sysemu/cp0_helper.c | 2 +- target/mips/tcg/sysemu/tlb_helper.c | 2 +- target/openrisc/mmu.c | 2 +- target/openrisc/sys_helper.c | 1 + target/ppc/helper_regs.c | 2 +- target/ppc/misc_helper.c | 1 + target/ppc/mmu_helper.c | 1 + target/riscv/cpu_helper.c | 2 +- target/riscv/csr.c | 1 + target/riscv/op_helper.c | 1 + target/riscv/pmp.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/gdbstub.c | 2 +- target/s390x/sigp.c | 2 +- target/s390x/tcg/excp_helper.c | 1 + target/s390x/tcg/mem_helper.c | 1 + target/s390x/tcg/misc_helper.c | 1 + target/sh4/helper.c | 2 +- target/sparc/ldst_helper.c | 1 + target/tricore/helper.c | 2 +- target/xtensa/helper.c | 2 +- target/xtensa/mmu_helper.c | 1 + 46 files changed, 231 insertions(+), 210 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 9075d94ec5..07c4bc669e 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -39,6 +39,141 @@ void tlb_init(CPUState *cpu); */ void tlb_destroy(CPUState *cpu); =20 +/** + * tlb_flush_page: + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of page to be flushed + * + * Flush one page from the TLB of the specified CPU, for all + * MMU indexes. + */ +void tlb_flush_page(CPUState *cpu, vaddr addr); + +/** + * tlb_flush_page_all_cpus_synced: + * @cpu: src CPU of the flush + * @addr: virtual address of page to be flushed + * + * Flush one page from the TLB of all CPUs, for all + * MMU indexes. + * + * When this function returns, no CPUs will subsequently perform + * translations using the flushed TLBs. + */ +void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr); + +/** + * tlb_flush: + * @cpu: CPU whose TLB should be flushed + * + * Flush the entire TLB for the specified CPU. Most CPU architectures + * allow the implementation to drop entries from the TLB at any time + * so this is generally safe. If more selective flushing is required + * use one of the other functions for efficiency. + */ +void tlb_flush(CPUState *cpu); + +/** + * tlb_flush_all_cpus_synced: + * @cpu: src CPU of the flush + * + * Flush the entire TLB for all CPUs, for all MMU indexes. + * + * When this function returns, no CPUs will subsequently perform + * translations using the flushed TLBs. + */ +void tlb_flush_all_cpus_synced(CPUState *src_cpu); + +/** + * tlb_flush_page_by_mmuidx: + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of page to be flushed + * @idxmap: bitmap of MMU indexes to flush + * + * Flush one page from the TLB of the specified CPU, for the specified + * MMU indexes. + */ +void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr, + uint16_t idxmap); + +/** + * tlb_flush_page_by_mmuidx_all_cpus_synced: + * @cpu: Originating CPU of the flush + * @addr: virtual address of page to be flushed + * @idxmap: bitmap of MMU indexes to flush + * + * Flush one page from the TLB of all CPUs, for the specified + * MMU indexes. + * + * When this function returns, no CPUs will subsequently perform + * translations using the flushed TLBs. + */ +void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, + uint16_t idxmap); + +/** + * tlb_flush_by_mmuidx: + * @cpu: CPU whose TLB should be flushed + * @wait: If true ensure synchronisation by exiting the cpu_loop + * @idxmap: bitmap of MMU indexes to flush + * + * Flush all entries from the TLB of the specified CPU, for the specified + * MMU indexes. + */ +void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap); + +/** + * tlb_flush_by_mmuidx_all_cpus_synced: + * @cpu: Originating CPU of the flush + * @idxmap: bitmap of MMU indexes to flush + * + * Flush all entries from the TLB of all CPUs, for the specified + * MMU indexes. + * + * When this function returns, no CPUs will subsequently perform + * translations using the flushed TLBs. + */ +void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap); + +/** + * tlb_flush_page_bits_by_mmuidx + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of page to be flushed + * @idxmap: bitmap of mmu indexes to flush + * @bits: number of significant bits in address + * + * Similar to tlb_flush_page_mask, but with a bitmap of indexes. + */ +void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr, + uint16_t idxmap, unsigned bits); + +/* Similarly, with broadcast and syncing. */ +void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr ad= dr, + uint16_t idxmap, + unsigned bits); + +/** + * tlb_flush_range_by_mmuidx + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of the start of the range to be flushed + * @len: length of range to be flushed + * @idxmap: bitmap of mmu indexes to flush + * @bits: number of significant bits in address + * + * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len), + * comparing only the low @bits worth of each virtual page. + */ +void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, + vaddr len, uint16_t idxmap, + unsigned bits); + +/* Similarly, with broadcast and syncing. */ +void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, + vaddr addr, + vaddr len, + uint16_t idxmap, + unsigned bits); + void tlb_protect_code(ram_addr_t ram_addr); void tlb_unprotect_code(ram_addr_t ram_addr); =20 @@ -50,6 +185,58 @@ static inline void tlb_init(CPUState *cpu) static inline void tlb_destroy(CPUState *cpu) { } +static inline void tlb_flush_page(CPUState *cpu, vaddr addr) +{ +} +static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr add= r) +{ +} +static inline void tlb_flush(CPUState *cpu) +{ +} +static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu) +{ +} +static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, + vaddr addr, uint16_t idxmap) +{ +} + +static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) +{ +} +static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, + vaddr addr, + uint16_t idxma= p) +{ +} +static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, + uint16_t idxmap) +{ +} +static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, + vaddr addr, + uint16_t idxmap, + unsigned bits) +{ +} +static inline void +tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, + uint16_t idxmap, unsigned bi= ts) +{ +} +static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, + vaddr len, uint16_t idxmap, + unsigned bits) +{ +} +static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, + vaddr addr, + vaddr len, + uint16_t idxm= ap, + unsigned bits) +{ +} =20 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ =20 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 2e58540005..36dbc191cd 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -46,189 +46,6 @@ static inline bool cpu_loop_exit_requested(CPUState *cp= u) return (int32_t)qatomic_read(&cpu->neg.icount_decr.u32) < 0; } =20 -#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) -/** - * tlb_flush_page: - * @cpu: CPU whose TLB should be flushed - * @addr: virtual address of page to be flushed - * - * Flush one page from the TLB of the specified CPU, for all - * MMU indexes. - */ -void tlb_flush_page(CPUState *cpu, vaddr addr); -/** - * tlb_flush_page_all_cpus_synced: - * @cpu: src CPU of the flush - * @addr: virtual address of page to be flushed - * - * Flush one page from the TLB of all CPUs, for all - * MMU indexes. - * - * When this function returns, no CPUs will subsequently perform - * translations using the flushed TLBs. - */ -void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr); -/** - * tlb_flush: - * @cpu: CPU whose TLB should be flushed - * - * Flush the entire TLB for the specified CPU. Most CPU architectures - * allow the implementation to drop entries from the TLB at any time - * so this is generally safe. If more selective flushing is required - * use one of the other functions for efficiency. - */ -void tlb_flush(CPUState *cpu); -/** - * tlb_flush_all_cpus_synced: - * @cpu: src CPU of the flush - * - * Flush the entire TLB for all CPUs, for all MMU indexes. - * - * When this function returns, no CPUs will subsequently perform - * translations using the flushed TLBs. - */ -void tlb_flush_all_cpus_synced(CPUState *src_cpu); -/** - * tlb_flush_page_by_mmuidx: - * @cpu: CPU whose TLB should be flushed - * @addr: virtual address of page to be flushed - * @idxmap: bitmap of MMU indexes to flush - * - * Flush one page from the TLB of the specified CPU, for the specified - * MMU indexes. - */ -void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr, - uint16_t idxmap); -/** - * tlb_flush_page_by_mmuidx_all_cpus_synced: - * @cpu: Originating CPU of the flush - * @addr: virtual address of page to be flushed - * @idxmap: bitmap of MMU indexes to flush - * - * Flush one page from the TLB of all CPUs, for the specified - * MMU indexes. - * - * When this function returns, no CPUs will subsequently perform - * translations using the flushed TLBs. - */ -void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, - uint16_t idxmap); -/** - * tlb_flush_by_mmuidx: - * @cpu: CPU whose TLB should be flushed - * @wait: If true ensure synchronisation by exiting the cpu_loop - * @idxmap: bitmap of MMU indexes to flush - * - * Flush all entries from the TLB of the specified CPU, for the specified - * MMU indexes. - */ -void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap); -/** - * tlb_flush_by_mmuidx_all_cpus_synced: - * @cpu: Originating CPU of the flush - * @idxmap: bitmap of MMU indexes to flush - * - * Flush all entries from the TLB of all CPUs, for the specified - * MMU indexes. - * - * When this function returns, no CPUs will subsequently perform - * translations using the flushed TLBs. - */ -void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap); - -/** - * tlb_flush_page_bits_by_mmuidx - * @cpu: CPU whose TLB should be flushed - * @addr: virtual address of page to be flushed - * @idxmap: bitmap of mmu indexes to flush - * @bits: number of significant bits in address - * - * Similar to tlb_flush_page_mask, but with a bitmap of indexes. - */ -void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr, - uint16_t idxmap, unsigned bits); - -/* Similarly, with broadcast and syncing. */ -void tlb_flush_page_bits_by_mmuidx_all_cpus_synced - (CPUState *cpu, vaddr addr, uint16_t idxmap, unsigned bits); - -/** - * tlb_flush_range_by_mmuidx - * @cpu: CPU whose TLB should be flushed - * @addr: virtual address of the start of the range to be flushed - * @len: length of range to be flushed - * @idxmap: bitmap of mmu indexes to flush - * @bits: number of significant bits in address - * - * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len), - * comparing only the low @bits worth of each virtual page. - */ -void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, - vaddr len, uint16_t idxmap, - unsigned bits); - -/* Similarly, with broadcast and syncing. */ -void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, - vaddr addr, - vaddr len, - uint16_t idxmap, - unsigned bits); - -#else -static inline void tlb_flush_page(CPUState *cpu, vaddr addr) -{ -} -static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr add= r) -{ -} -static inline void tlb_flush(CPUState *cpu) -{ -} -static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu) -{ -} -static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, - vaddr addr, uint16_t idxmap) -{ -} - -static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) -{ -} -static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, - vaddr addr, - uint16_t idxma= p) -{ -} -static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, - uint16_t idxmap) -{ -} -static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, - vaddr addr, - uint16_t idxmap, - unsigned bits) -{ -} -static inline void -tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, - uint16_t idxmap, unsigned bi= ts) -{ -} -static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, - vaddr len, uint16_t idxmap, - unsigned bits) -{ -} -static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, - vaddr addr, - vaddr len, - uint16_t idxm= ap, - unsigned bits) -{ -} -#endif - #if defined(CONFIG_TCG) =20 /** diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 22486c5dff..663831700d 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -33,6 +33,7 @@ #include "qemu/guest-random.h" #include "qemu/timer.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/hwaddr.h" #include "exec/tb-flush.h" #include "exec/translation-block.h" diff --git a/cpu-target.c b/cpu-target.c index 499facf774..63d563cd0b 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -40,6 +40,7 @@ #include "exec/replay-core.h" #include "exec/cpu-common.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/tb-flush.h" #include "exec/translate-all.h" #include "exec/log.h" diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 98f3cf59bc..b0a638e035 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -22,7 +22,7 @@ #include "sysemu/runstate.h" #include "target/arm/cpu.h" #include "target/arm/cpu-features.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/memop.h" #include "qemu/log.h" #include "qemu/module.h" diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c index 7def8eb73b..23958c6383 100644 --- a/hw/ppc/spapr_nested.c +++ b/hw/ppc/spapr_nested.c @@ -1,6 +1,7 @@ #include "qemu/osdep.h" #include "qemu/cutils.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "helper_regs.h" #include "hw/ppc/ppc.h" #include "hw/ppc/spapr.h" diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index 8041b3b651..9692d5b624 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -36,6 +36,7 @@ #include "hw/sh4/sh_intc.h" #include "hw/timer/tmu012.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "trace.h" =20 typedef struct SH7750State { diff --git a/system/watchpoint.c b/system/watchpoint.c index f7366574a3..622463e11b 100644 --- a/system/watchpoint.c +++ b/system/watchpoint.c @@ -19,8 +19,8 @@ =20 #include "qemu/osdep.h" #include "qemu/error-report.h" -#include "exec/exec-all.h" #include "exec/cpu-all.h" +#include "exec/cputlb.h" #include "hw/core/cpu.h" =20 /* Add a watchpoint. */ diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 2f1000c99f..57cefcba14 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "fpu/softfloat-types.h" #include "exec/helper-proto.h" diff --git a/target/alpha/sys_helper.c b/target/alpha/sys_helper.c index 768116ef32..95cf3d2560 100644 --- a/target/alpha/sys_helper.c +++ b/target/alpha/sys_helper.c @@ -19,7 +19,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/tb-flush.h" #include "exec/helper-proto.h" #include "sysemu/runstate.h" diff --git a/target/arm/helper.c b/target/arm/helper.c index f38eb054c0..c2e400643a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -19,6 +19,7 @@ #include "qemu/crc32c.h" #include "qemu/qemu-print.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include /* for crc32 */ #include "hw/irq.h" #include "sysemu/cpu-timers.h" diff --git a/target/avr/helper.c b/target/avr/helper.c index 345708a1b3..f255126016 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -23,7 +23,7 @@ #include "qemu/error-report.h" #include "cpu.h" #include "hw/core/tcg-cpu-ops.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" #include "exec/address-spaces.h" diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index b8c3e55170..7a1729ccd2 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/helper-proto.h" #include "hw/core/cpu.h" diff --git a/target/i386/helper.c b/target/i386/helper.c index 75c52e2143..84a17172ba 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -21,6 +21,7 @@ #include "qapi/qapi-events-run-state.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/translation-block.h" #include "sysemu/runstate.h" #ifndef CONFIG_USER_ONLY diff --git a/target/i386/machine.c b/target/i386/machine.c index b4610325aa..2a08b26a4b 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -1,6 +1,6 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "hw/isa/isa.h" #include "migration/cpu.h" #include "kvm/hyperv.h" diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 53b49bb297..868d12381f 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -21,7 +21,7 @@ #include #include "cpu.h" #include "tcg-cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c index ed4cda8001..2b5f092a23 100644 --- a/target/i386/tcg/misc_helper.c +++ b/target/i386/tcg/misc_helper.c @@ -21,7 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "helper-tcg.h" =20 /* diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/= misc_helper.c index 094aa56a20..75cd592267 100644 --- a/target/i386/tcg/sysemu/misc_helper.c +++ b/target/i386/tcg/sysemu/misc_helper.c @@ -23,7 +23,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/address-spaces.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "tcg/helper-tcg.h" #include "hw/i386/apic.h" =20 diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/s= vm_helper.c index 9db8ad62a0..0def3afb14 100644 --- a/target/i386/tcg/sysemu/svm_helper.c +++ b/target/i386/tcg/sysemu/svm_helper.c @@ -21,7 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "tcg/helper-tcg.h" =20 diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_h= elper.c index 15f94caefa..d486b8f23b 100644 --- a/target/loongarch/tcg/csr_helper.c +++ b/target/loongarch/tcg/csr_helper.c @@ -11,7 +11,7 @@ #include "internals.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "hw/irq.h" #include "cpu-csr.h" diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 97f38fc391..40603202e5 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -12,7 +12,7 @@ #include "cpu.h" #include "internals.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" #include "exec/log.h" diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 9bfc6ae97c..fc8ea87ddb 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -20,7 +20,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/gdbstub.h" #include "exec/helper-proto.h" diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 2423ac6172..f8587d5ac4 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" =20 static unsigned int tlb_decode_size(unsigned int f) diff --git a/target/mips/sysemu/cp0.c b/target/mips/sysemu/cp0.c index bae37f515b..ff7d3db00c 100644 --- a/target/mips/sysemu/cp0.c +++ b/target/mips/sysemu/cp0.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internal.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" =20 /* Called for updates to CP0_Status. */ void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) diff --git a/target/mips/tcg/sysemu/cp0_helper.c b/target/mips/tcg/sysemu/c= p0_helper.c index 79a5c833ce..01a07a169f 100644 --- a/target/mips/tcg/sysemu/cp0_helper.c +++ b/target/mips/tcg/sysemu/cp0_helper.c @@ -27,7 +27,7 @@ #include "internal.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" =20 =20 /* SMP helpers. */ diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/t= lb_helper.c index e98bb95951..b545d49a6b 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -21,7 +21,7 @@ =20 #include "cpu.h" #include "internal.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" #include "exec/log.h" diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index c632d5230b..47ac783c52 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "gdbstub/helpers.h" #include "qemu/host-utils.h" diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 77567afba4..21bc137ccc 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/helper-proto.h" #include "exception.h" #ifndef CONFIG_USER_ONLY diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 42c681ca4a..61432c165b 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "qemu/main-loop.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "sysemu/kvm.h" #include "sysemu/tcg.h" #include "helper_regs.h" diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index f0ca80153b..e379da6010 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -21,6 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/helper-proto.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index b167b37e0a..718070b600 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -24,6 +24,7 @@ #include "kvm_ppc.h" #include "mmu-hash64.h" #include "mmu-hash32.h" +#include "exec/cputlb.h" #include "exec/exec-all.h" #include "exec/page-protection.h" #include "exec/log.h" diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 0a3ead69ea..767db4a5cc 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -23,7 +23,7 @@ #include "cpu.h" #include "internals.h" #include "pmu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "instmap.h" #include "tcg/tcg-op.h" diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9846770820..9e1c4ab0e7 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -25,6 +25,7 @@ #include "pmu.h" #include "time_helper.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/tb-flush.h" #include "sysemu/cpu-timers.h" #include "qemu/guest-random.h" diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index eddedacf4b..212ba97408 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" =20 diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index a1b36664fc..1bf962cf1b 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -24,7 +24,7 @@ #include "qapi/error.h" #include "cpu.h" #include "trace.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" =20 static bool pmp_write_cfg(CPURISCVState *env, uint32_t addr_index, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 945ae6e9e5..add51d4477 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -21,7 +21,7 @@ #include "qapi/error.h" #include "cpu.h" #include "migration/vmstate.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/translation-block.h" #include "hw/loader.h" diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c index 63373f02ce..865313c98f 100644 --- a/target/s390x/gdbstub.c +++ b/target/s390x/gdbstub.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "s390x-internal.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/gdbstub.h" #include "gdbstub/helpers.h" #include "qemu/bitops.h" diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c index 08aaecf12b..0d18f14251 100644 --- a/target/s390x/sigp.c +++ b/target/s390x/sigp.c @@ -15,7 +15,7 @@ #include "sysemu/hw_accel.h" #include "sysemu/runstate.h" #include "exec/address-spaces.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "sysemu/tcg.h" #include "trace.h" #include "qapi/qapi-types-machine.h" diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index 4c0b692c9e..003ed86413 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "s390x-internal.h" #include "tcg_s390x.h" #ifndef CONFIG_USER_ONLY diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 0e12dae2aa..2ad54d7133 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -25,6 +25,7 @@ #include "tcg_s390x.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" #include "hw/core/tcg-cpu-ops.h" diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c index 303f86d363..e3401f4efe 100644 --- a/target/s390x/tcg/misc_helper.c +++ b/target/s390x/tcg/misc_helper.c @@ -27,6 +27,7 @@ #include "exec/helper-proto.h" #include "qemu/timer.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/cpu_ldst.h" #include "qapi/error.h" #include "tcg_s390x.h" diff --git a/target/sh4/helper.c b/target/sh4/helper.c index 9659c69550..a45c38cc4d 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" =20 #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/log.h" =20 diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index d92c9f1593..ae2a5fb4ab 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -24,6 +24,7 @@ #include "tcg/tcg.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/cpu_ldst.h" #include "asi.h" diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 7014255f77..d88dd20305 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -19,7 +19,7 @@ #include "qemu/log.h" #include "hw/registerfields.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" #include "fpu/softfloat-helpers.h" #include "qemu/qemu-print.h" diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index ca214b948a..6327bf048f 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -28,7 +28,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" -#include "exec/exec-all.h" +#include "exec/cputlb.h" #include "gdbstub/helpers.h" #include "exec/helper-proto.h" #include "qemu/error-report.h" diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 29b84d5dbf..91b869fb50 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -33,6 +33,7 @@ #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" +#include "exec/cputlb.h" #include "exec/page-protection.h" =20 #define XTENSA_MPU_SEGMENT_MASK 0x0000001f --=20 2.45.2 From nobody Sat Nov 23 17:19:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1731547194; cv=none; d=zohomail.com; s=zohoarc; b=FBbeqRUCYNo2d4epSNTXE2okhH75EZ8T2Bk1PlzFvd1K1Sz5u1yZ9ZgAIuies/9aFHpik6+aOg+3V8E2AQNRlewtnFlAa9EsiWsK0WCcO9LRuSdORN9Zfoc1Dvbulp5xo9o5uRXtfMmw59R76hsy7vqOLqIGTKyZIu5MhYb5F3g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1731547194; 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qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 19/24] exec: Declare tlb_hit*() in 'exec/cputlb.h' Date: Thu, 14 Nov 2024 02:13:04 +0100 Message-ID: <20241114011310.3615-20-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731547196346116600 Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/exec/cpu-all.h | 23 ----------------------- accel/tcg/cputlb.c | 23 +++++++++++++++++++++++ 2 files changed, 23 insertions(+), 23 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 1c8e0446d0..ccaa650b19 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -323,29 +323,6 @@ static inline int cpu_mmu_index(CPUState *cs, bool ife= tch) /* The two sets of flags must not overlap. */ QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); =20 -/** - * tlb_hit_page: return true if page aligned @addr is a hit against the - * TLB entry @tlb_addr - * - * @addr: virtual address to test (must be page aligned) - * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) - */ -static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr) -{ - return addr =3D=3D (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); -} - -/** - * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr - * - * @addr: virtual address to test (need not be page aligned) - * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) - */ -static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr) -{ - return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); -} - #endif /* !CONFIG_USER_ONLY */ =20 /* Validate correct placement of CPUArchState. */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 080cbcb34d..dba4831cd1 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1220,6 +1220,29 @@ void tlb_set_page(CPUState *cpu, vaddr addr, prot, mmu_idx, size); } =20 +/** + * tlb_hit_page: return true if page aligned @addr is a hit against the + * TLB entry @tlb_addr + * + * @addr: virtual address to test (must be page aligned) + * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) + */ +static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr) +{ + return addr =3D=3D (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); +} + +/** + * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr + * + * @addr: virtual address to test (need not be page aligned) + * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) + */ +static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr) +{ + return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); +} + /* * Note: tlb_fill_align() can trigger a resize of the TLB. * This means that all of the caller's prior references to the TLB table --=20 2.45.2 From nobody Sat Nov 23 17:19:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1731547051; cv=none; d=zohomail.com; s=zohoarc; b=EaugZ45bm0Ru5JTgQYTZpvSg0SLh+6+evdvh2pFN4fMOdVcfhZSZl7ANHPTcGLr7D9LOI/NkchwVv1Jnm/Ly1HSMl1T6PjxjuBxNjPxAQHWSdN04tZcOPj9wJ/wJUxxahXNQhQtuwo3Y2tBgDAm6hFWjiOJx+hZAERTgG4W0zNQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1731547051; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Wed, 13 Nov 2024 17:15:55 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 20/24] exec: Declare tlb_vaddr_to_host() in 'exec/cputlb.h' Date: Thu, 14 Nov 2024 02:13:05 +0100 Message-ID: <20241114011310.3615-21-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731547051776116600 Move CPU TLB related methods to "exec/cputlb.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- include/exec/cpu_ldst.h | 25 ------------------------- include/exec/cputlb.h | 26 ++++++++++++++++++++++++++ target/arm/tcg/helper-a64.c | 1 + target/ppc/mem_helper.c | 1 + 4 files changed, 28 insertions(+), 25 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 769e9fc440..eec47ca05e 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -69,7 +69,6 @@ #include "exec/memopidx.h" #include "exec/vaddr.h" #include "exec/abi_ptr.h" -#include "exec/mmu-access-type.h" #include "qemu/int128.h" =20 #if defined(CONFIG_USER_ONLY) @@ -311,30 +310,6 @@ uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr= ); uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr); uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr); =20 -/** - * tlb_vaddr_to_host: - * @env: CPUArchState - * @addr: guest virtual address to look up - * @access_type: 0 for read, 1 for write, 2 for execute - * @mmu_idx: MMU index to use for lookup - * - * Look up the specified guest virtual index in the TCG softmmu TLB. - * If we can translate a host virtual address suitable for direct RAM - * access, without causing a guest exception, then return it. - * Otherwise (TLB entry is for an I/O access, guest software - * TLB fill required, etc) return NULL. - */ -#ifdef CONFIG_USER_ONLY -static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, - MMUAccessType access_type, int mmu_i= dx) -{ - return g2h(env_cpu(env), addr); -} -#else -void *tlb_vaddr_to_host(CPUArchState *env, vaddr addr, - MMUAccessType access_type, int mmu_idx); -#endif - /* * For user-only, helpers that use guest to host address translation * must protect the actual host memory access by recording 'retaddr' diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 07c4bc669e..4acc2c6235 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -20,6 +20,7 @@ #ifndef CPUTLB_H #define CPUTLB_H =20 +#include "exec/abi_ptr.h" #include "exec/cpu-common.h" #include "exec/hwaddr.h" #include "exec/memattrs.h" @@ -306,4 +307,29 @@ void tlb_set_page(CPUState *cpu, vaddr addr, hwaddr paddr, int prot, int mmu_idx, vaddr size); =20 +/** + * tlb_vaddr_to_host: + * @env: CPUArchState + * @addr: guest virtual address to look up + * @access_type: 0 for read, 1 for write, 2 for execute + * @mmu_idx: MMU index to use for lookup + * + * Look up the specified guest virtual index in the TCG softmmu TLB. + * If we can translate a host virtual address suitable for direct RAM + * access, without causing a guest exception, then return it. + * Otherwise (TLB entry is for an I/O access, guest software + * TLB fill required, etc) return NULL. + */ +#ifdef CONFIG_USER_ONLY +#include "user/guest-host.h" +static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, + MMUAccessType access_type, int mmu_i= dx) +{ + return g2h(env_cpu(env), addr); +} +#else +void *tlb_vaddr_to_host(CPUArchState *env, vaddr addr, + MMUAccessType access_type, int mmu_idx); +#endif + #endif diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 8f42a28d07..9cb5d8ee53 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -30,6 +30,7 @@ #include "qemu/crc32c.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "exec/cputlb.h" #include "qemu/int128.h" #include "qemu/atomic128.h" #include "fpu/softfloat.h" diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 51b137febd..44974b25f8 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -24,6 +24,7 @@ #include "exec/helper-proto.h" #include "helper_regs.h" #include "exec/cpu_ldst.h" +#include "exec/cputlb.h" #include "internal.h" #include "qemu/atomic128.h" =20 --=20 2.45.2 From nobody Sat Nov 23 17:19:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731547128180116600 In order to keep "exec/ram_addr.h" focused on (target agnostic) methods related to the ram_addr_t type, move all (target specific) CPU physical memory API to a new "sysemu/physmem-target.h" header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- MAINTAINERS | 1 + include/exec/ram_addr.h | 483 +--------------------------- include/sysemu/physmem-target.h | 506 ++++++++++++++++++++++++++++++ accel/kvm/kvm-all.c | 1 + accel/tcg/cputlb.c | 1 + accel/tcg/translate-all.c | 1 + hw/ppc/spapr.c | 1 + hw/ppc/spapr_caps.c | 1 + hw/ppc/spapr_pci.c | 1 + hw/remote/memory.c | 1 + hw/remote/proxy-memory-listener.c | 1 + hw/s390x/s390-stattrib-kvm.c | 1 + hw/s390x/s390-stattrib.c | 1 + hw/s390x/s390-virtio-ccw.c | 1 + hw/vfio/common.c | 1 + hw/vfio/container.c | 1 + hw/vfio/iommufd.c | 1 + hw/vfio/migration.c | 1 + hw/vfio/spapr.c | 1 + hw/virtio/virtio-mem.c | 1 + migration/ram.c | 1 + plugins/api.c | 1 + system/memory.c | 1 + system/physmem.c | 1 + target/arm/tcg/mte_helper.c | 1 + target/ppc/kvm.c | 1 + target/s390x/kvm/kvm.c | 1 + 27 files changed, 532 insertions(+), 482 deletions(-) create mode 100644 include/sysemu/physmem-target.h diff --git a/MAINTAINERS b/MAINTAINERS index 095420f8b0..0027e56fa5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3027,6 +3027,7 @@ F: include/exec/memory.h F: include/exec/ram_addr.h F: include/exec/ramblock.h F: include/sysemu/memory_mapping.h +F: include/sysemu/physmem-target.h F: system/dma-helpers.c F: system/ioport.c F: system/memory.c diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index b6d5551549..80f6dc7564 100644 --- a/include/exec/ram_addr.h +++ b/include/exec/ram_addr.h @@ -20,82 +20,6 @@ #define RAM_ADDR_H =20 #ifndef CONFIG_USER_ONLY -#include "cpu.h" -#include "sysemu/xen.h" -#include "sysemu/tcg.h" -#include "exec/cputlb.h" -#include "exec/ramlist.h" -#include "exec/ramblock.h" -#include "exec/exec-all.h" -#include "qemu/rcu.h" - -extern uint64_t total_dirty_pages; - -/** - * clear_bmap_size: calculate clear bitmap size - * - * @pages: number of guest pages - * @shift: guest page number shift - * - * Returns: number of bits for the clear bitmap - */ -static inline long clear_bmap_size(uint64_t pages, uint8_t shift) -{ - return DIV_ROUND_UP(pages, 1UL << shift); -} - -/** - * clear_bmap_set: set clear bitmap for the page range. Must be with - * bitmap_mutex held. - * - * @rb: the ramblock to operate on - * @start: the start page number - * @size: number of pages to set in the bitmap - * - * Returns: None - */ -static inline void clear_bmap_set(RAMBlock *rb, uint64_t start, - uint64_t npages) -{ - uint8_t shift =3D rb->clear_bmap_shift; - - bitmap_set(rb->clear_bmap, start >> shift, clear_bmap_size(npages, shi= ft)); -} - -/** - * clear_bmap_test_and_clear: test clear bitmap for the page, clear if set. - * Must be with bitmap_mutex held. - * - * @rb: the ramblock to operate on - * @page: the page number to check - * - * Returns: true if the bit was set, false otherwise - */ -static inline bool clear_bmap_test_and_clear(RAMBlock *rb, uint64_t page) -{ - uint8_t shift =3D rb->clear_bmap_shift; - - return bitmap_test_and_clear(rb->clear_bmap, page >> shift, 1); -} - -static inline bool offset_in_ramblock(RAMBlock *b, ram_addr_t offset) -{ - return (b && b->host && offset < b->used_length) ? true : false; -} - -static inline void *ramblock_ptr(RAMBlock *block, ram_addr_t offset) -{ - assert(offset_in_ramblock(block, offset)); - return (char *)block->host + offset; -} - -static inline unsigned long int ramblock_recv_bitmap_offset(void *host_add= r, - RAMBlock *rb) -{ - uint64_t host_addr_offset =3D - (uint64_t)(uintptr_t)(host_addr - (void *)rb->host); - return host_addr_offset >> TARGET_PAGE_BITS; -} =20 bool ramblock_is_pmem(RAMBlock *rb); =20 @@ -143,411 +67,6 @@ int qemu_ram_resize(RAMBlock *block, ram_addr_t newsiz= e, Error **errp); =20 void qemu_ram_msync(RAMBlock *block, ram_addr_t start, ram_addr_t length); =20 -/* Clear whole block of mem */ -static inline void qemu_ram_block_writeback(RAMBlock *block) -{ - qemu_ram_msync(block, 0, block->used_length); -} +#endif /* CONFIG_USER_ONLY */ =20 -#define DIRTY_CLIENTS_ALL ((1 << DIRTY_MEMORY_NUM) - 1) -#define DIRTY_CLIENTS_NOCODE (DIRTY_CLIENTS_ALL & ~(1 << DIRTY_MEMORY_COD= E)) - -static inline bool cpu_physical_memory_get_dirty(ram_addr_t start, - ram_addr_t length, - unsigned client) -{ - DirtyMemoryBlocks *blocks; - unsigned long end, page; - unsigned long idx, offset, base; - bool dirty =3D false; - - assert(client < DIRTY_MEMORY_NUM); - - end =3D TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS; - page =3D start >> TARGET_PAGE_BITS; - - WITH_RCU_READ_LOCK_GUARD() { - blocks =3D qatomic_rcu_read(&ram_list.dirty_memory[client]); - - idx =3D page / DIRTY_MEMORY_BLOCK_SIZE; - offset =3D page % DIRTY_MEMORY_BLOCK_SIZE; - base =3D page - offset; - while (page < end) { - unsigned long next =3D MIN(end, base + DIRTY_MEMORY_BLOCK_SIZE= ); - unsigned long num =3D next - base; - unsigned long found =3D find_next_bit(blocks->blocks[idx], - num, offset); - if (found < num) { - dirty =3D true; - break; - } - - page =3D next; - idx++; - offset =3D 0; - base +=3D DIRTY_MEMORY_BLOCK_SIZE; - } - } - - return dirty; -} - -static inline bool cpu_physical_memory_all_dirty(ram_addr_t start, - ram_addr_t length, - unsigned client) -{ - DirtyMemoryBlocks *blocks; - unsigned long end, page; - unsigned long idx, offset, base; - bool dirty =3D true; - - assert(client < DIRTY_MEMORY_NUM); - - end =3D TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS; - page =3D start >> TARGET_PAGE_BITS; - - RCU_READ_LOCK_GUARD(); - - blocks =3D qatomic_rcu_read(&ram_list.dirty_memory[client]); - - idx =3D page / DIRTY_MEMORY_BLOCK_SIZE; - offset =3D page % DIRTY_MEMORY_BLOCK_SIZE; - base =3D page - offset; - while (page < end) { - unsigned long next =3D MIN(end, base + DIRTY_MEMORY_BLOCK_SIZE); - unsigned long num =3D next - base; - unsigned long found =3D find_next_zero_bit(blocks->blocks[idx], nu= m, offset); - if (found < num) { - dirty =3D false; - break; - } - - page =3D next; - idx++; - offset =3D 0; - base +=3D DIRTY_MEMORY_BLOCK_SIZE; - } - - return dirty; -} - -static inline bool cpu_physical_memory_get_dirty_flag(ram_addr_t addr, - unsigned client) -{ - return cpu_physical_memory_get_dirty(addr, 1, client); -} - -static inline bool cpu_physical_memory_is_clean(ram_addr_t addr) -{ - bool vga =3D cpu_physical_memory_get_dirty_flag(addr, DIRTY_MEMORY_VGA= ); - bool code =3D cpu_physical_memory_get_dirty_flag(addr, DIRTY_MEMORY_CO= DE); - bool migration =3D - cpu_physical_memory_get_dirty_flag(addr, DIRTY_MEMORY_MIGRATION); - return !(vga && code && migration); -} - -static inline uint8_t cpu_physical_memory_range_includes_clean(ram_addr_t = start, - ram_addr_t = length, - uint8_t mas= k) -{ - uint8_t ret =3D 0; - - if (mask & (1 << DIRTY_MEMORY_VGA) && - !cpu_physical_memory_all_dirty(start, length, DIRTY_MEMORY_VGA)) { - ret |=3D (1 << DIRTY_MEMORY_VGA); - } - if (mask & (1 << DIRTY_MEMORY_CODE) && - !cpu_physical_memory_all_dirty(start, length, DIRTY_MEMORY_CODE)) { - ret |=3D (1 << DIRTY_MEMORY_CODE); - } - if (mask & (1 << DIRTY_MEMORY_MIGRATION) && - !cpu_physical_memory_all_dirty(start, length, DIRTY_MEMORY_MIGRATI= ON)) { - ret |=3D (1 << DIRTY_MEMORY_MIGRATION); - } - return ret; -} - -static inline void cpu_physical_memory_set_dirty_flag(ram_addr_t addr, - unsigned client) -{ - unsigned long page, idx, offset; - DirtyMemoryBlocks *blocks; - - assert(client < DIRTY_MEMORY_NUM); - - page =3D addr >> TARGET_PAGE_BITS; - idx =3D page / DIRTY_MEMORY_BLOCK_SIZE; - offset =3D page % DIRTY_MEMORY_BLOCK_SIZE; - - RCU_READ_LOCK_GUARD(); - - blocks =3D qatomic_rcu_read(&ram_list.dirty_memory[client]); - - set_bit_atomic(offset, blocks->blocks[idx]); -} - -static inline void cpu_physical_memory_set_dirty_range(ram_addr_t start, - ram_addr_t length, - uint8_t mask) -{ - DirtyMemoryBlocks *blocks[DIRTY_MEMORY_NUM]; - unsigned long end, page; - unsigned long idx, offset, base; - int i; - - if (!mask && !xen_enabled()) { - return; - } - - end =3D TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS; - page =3D start >> TARGET_PAGE_BITS; - - WITH_RCU_READ_LOCK_GUARD() { - for (i =3D 0; i < DIRTY_MEMORY_NUM; i++) { - blocks[i] =3D qatomic_rcu_read(&ram_list.dirty_memory[i]); - } - - idx =3D page / DIRTY_MEMORY_BLOCK_SIZE; - offset =3D page % DIRTY_MEMORY_BLOCK_SIZE; - base =3D page - offset; - while (page < end) { - unsigned long next =3D MIN(end, base + DIRTY_MEMORY_BLOCK_SIZE= ); - - if (likely(mask & (1 << DIRTY_MEMORY_MIGRATION))) { - bitmap_set_atomic(blocks[DIRTY_MEMORY_MIGRATION]->blocks[i= dx], - offset, next - page); - } - if (unlikely(mask & (1 << DIRTY_MEMORY_VGA))) { - bitmap_set_atomic(blocks[DIRTY_MEMORY_VGA]->blocks[idx], - offset, next - page); - } - if (unlikely(mask & (1 << DIRTY_MEMORY_CODE))) { - bitmap_set_atomic(blocks[DIRTY_MEMORY_CODE]->blocks[idx], - offset, next - page); - } - - page =3D next; - idx++; - offset =3D 0; - base +=3D DIRTY_MEMORY_BLOCK_SIZE; - } - } - - xen_hvm_modified_memory(start, length); -} - -#if !defined(_WIN32) - -/* - * Contrary to cpu_physical_memory_sync_dirty_bitmap() this function retur= ns - * the number of dirty pages in @bitmap passed as argument. On the other h= and, - * cpu_physical_memory_sync_dirty_bitmap() returns newly dirtied pages that - * weren't set in the global migration bitmap. - */ -static inline -uint64_t cpu_physical_memory_set_dirty_lebitmap(unsigned long *bitmap, - ram_addr_t start, - ram_addr_t pages) -{ - unsigned long i, j; - unsigned long page_number, c, nbits; - hwaddr addr; - ram_addr_t ram_addr; - uint64_t num_dirty =3D 0; - unsigned long len =3D (pages + HOST_LONG_BITS - 1) / HOST_LONG_BITS; - unsigned long hpratio =3D qemu_real_host_page_size() / TARGET_PAGE_SIZ= E; - unsigned long page =3D BIT_WORD(start >> TARGET_PAGE_BITS); - - /* start address is aligned at the start of a word? */ - if ((((page * BITS_PER_LONG) << TARGET_PAGE_BITS) =3D=3D start) && - (hpratio =3D=3D 1)) { - unsigned long **blocks[DIRTY_MEMORY_NUM]; - unsigned long idx; - unsigned long offset; - long k; - long nr =3D BITS_TO_LONGS(pages); - - idx =3D (start >> TARGET_PAGE_BITS) / DIRTY_MEMORY_BLOCK_SIZE; - offset =3D BIT_WORD((start >> TARGET_PAGE_BITS) % - DIRTY_MEMORY_BLOCK_SIZE); - - WITH_RCU_READ_LOCK_GUARD() { - for (i =3D 0; i < DIRTY_MEMORY_NUM; i++) { - blocks[i] =3D - qatomic_rcu_read(&ram_list.dirty_memory[i])->blocks; - } - - for (k =3D 0; k < nr; k++) { - if (bitmap[k]) { - unsigned long temp =3D leul_to_cpu(bitmap[k]); - - nbits =3D ctpopl(temp); - qatomic_or(&blocks[DIRTY_MEMORY_VGA][idx][offset], tem= p); - - if (global_dirty_tracking) { - qatomic_or( - &blocks[DIRTY_MEMORY_MIGRATION][idx][offse= t], - temp); - if (unlikely( - global_dirty_tracking & GLOBAL_DIRTY_DIRTY_RAT= E)) { - total_dirty_pages +=3D nbits; - } - } - - num_dirty +=3D nbits; - - if (tcg_enabled()) { - qatomic_or(&blocks[DIRTY_MEMORY_CODE][idx][offset], - temp); - } - } - - if (++offset >=3D BITS_TO_LONGS(DIRTY_MEMORY_BLOCK_SIZE)) { - offset =3D 0; - idx++; - } - } - } - - xen_hvm_modified_memory(start, pages << TARGET_PAGE_BITS); - } else { - uint8_t clients =3D tcg_enabled() ? DIRTY_CLIENTS_ALL : DIRTY_CLIE= NTS_NOCODE; - - if (!global_dirty_tracking) { - clients &=3D ~(1 << DIRTY_MEMORY_MIGRATION); - } - - /* - * bitmap-traveling is faster than memory-traveling (for addr...) - * especially when most of the memory is not dirty. - */ - for (i =3D 0; i < len; i++) { - if (bitmap[i] !=3D 0) { - c =3D leul_to_cpu(bitmap[i]); - nbits =3D ctpopl(c); - if (unlikely(global_dirty_tracking & GLOBAL_DIRTY_DIRTY_RA= TE)) { - total_dirty_pages +=3D nbits; - } - num_dirty +=3D nbits; - do { - j =3D ctzl(c); - c &=3D ~(1ul << j); - page_number =3D (i * HOST_LONG_BITS + j) * hpratio; - addr =3D page_number * TARGET_PAGE_SIZE; - ram_addr =3D start + addr; - cpu_physical_memory_set_dirty_range(ram_addr, - TARGET_PAGE_SIZE * hpratio, clients= ); - } while (c !=3D 0); - } - } - } - - return num_dirty; -} -#endif /* not _WIN32 */ - -static inline void cpu_physical_memory_dirty_bits_cleared(ram_addr_t start, - ram_addr_t lengt= h) -{ - if (tcg_enabled()) { - tlb_reset_dirty_range_all(start, length); - } - -} -bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start, - ram_addr_t length, - unsigned client); - -DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty - (MemoryRegion *mr, hwaddr offset, hwaddr length, unsigned client); - -bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap, - ram_addr_t start, - ram_addr_t length); - -static inline void cpu_physical_memory_clear_dirty_range(ram_addr_t start, - ram_addr_t length) -{ - cpu_physical_memory_test_and_clear_dirty(start, length, DIRTY_MEMORY_M= IGRATION); - cpu_physical_memory_test_and_clear_dirty(start, length, DIRTY_MEMORY_V= GA); - cpu_physical_memory_test_and_clear_dirty(start, length, DIRTY_MEMORY_C= ODE); -} - - -/* Called with RCU critical section */ -static inline -uint64_t cpu_physical_memory_sync_dirty_bitmap(RAMBlock *rb, - ram_addr_t start, - ram_addr_t length) -{ - ram_addr_t addr; - unsigned long word =3D BIT_WORD((start + rb->offset) >> TARGET_PAGE_BI= TS); - uint64_t num_dirty =3D 0; - unsigned long *dest =3D rb->bmap; - - /* start address and length is aligned at the start of a word? */ - if (((word * BITS_PER_LONG) << TARGET_PAGE_BITS) =3D=3D - (start + rb->offset) && - !(length & ((BITS_PER_LONG << TARGET_PAGE_BITS) - 1))) { - int k; - int nr =3D BITS_TO_LONGS(length >> TARGET_PAGE_BITS); - unsigned long * const *src; - unsigned long idx =3D (word * BITS_PER_LONG) / DIRTY_MEMORY_BLOCK_= SIZE; - unsigned long offset =3D BIT_WORD((word * BITS_PER_LONG) % - DIRTY_MEMORY_BLOCK_SIZE); - unsigned long page =3D BIT_WORD(start >> TARGET_PAGE_BITS); - - src =3D qatomic_rcu_read( - &ram_list.dirty_memory[DIRTY_MEMORY_MIGRATION])->blocks; - - for (k =3D page; k < page + nr; k++) { - if (src[idx][offset]) { - unsigned long bits =3D qatomic_xchg(&src[idx][offset], 0); - unsigned long new_dirty; - new_dirty =3D ~dest[k]; - dest[k] |=3D bits; - new_dirty &=3D bits; - num_dirty +=3D ctpopl(new_dirty); - } - - if (++offset >=3D BITS_TO_LONGS(DIRTY_MEMORY_BLOCK_SIZE)) { - offset =3D 0; - idx++; - } - } - if (num_dirty) { - cpu_physical_memory_dirty_bits_cleared(start, length); - } - - if (rb->clear_bmap) { - /* - * Postpone the dirty bitmap clear to the point before we - * really send the pages, also we will split the clear - * dirty procedure into smaller chunks. - */ - clear_bmap_set(rb, start >> TARGET_PAGE_BITS, - length >> TARGET_PAGE_BITS); - } else { - /* Slow path - still do that in a huge chunk */ - memory_region_clear_dirty_bitmap(rb->mr, start, length); - } - } else { - ram_addr_t offset =3D rb->offset; - - for (addr =3D 0; addr < length; addr +=3D TARGET_PAGE_SIZE) { - if (cpu_physical_memory_test_and_clear_dirty( - start + addr + offset, - TARGET_PAGE_SIZE, - DIRTY_MEMORY_MIGRATION)) { - long k =3D (start + addr) >> TARGET_PAGE_BITS; - if (!test_and_set_bit(k, dest)) { - num_dirty++; - } - } - } - } - - return num_dirty; -} -#endif #endif diff --git a/include/sysemu/physmem-target.h b/include/sysemu/physmem-targe= t.h new file mode 100644 index 0000000000..b30c42da60 --- /dev/null +++ b/include/sysemu/physmem-target.h @@ -0,0 +1,506 @@ +/* + * Declarations for cpu physical memory functions + * + * Copyright 2011 Red Hat, Inc. and/or its affiliates + * + * Authors: + * Avi Kivity + * + * This work is licensed under the terms of the GNU GPL, version 2 or + * later. See the COPYING file in the top-level directory. + * + */ + +/* + * This header is for use by exec.c and memory.c ONLY. Do not include it. + * The functions declared here will be removed soon. + */ + +#ifndef RAM_ADDR_TARGET_H +#define RAM_ADDR_TARGET_H + +#include "cpu.h" +#include "sysemu/xen.h" +#include "sysemu/tcg.h" +#include "exec/cputlb.h" +#include "exec/ram_addr.h" +#include "exec/ramlist.h" +#include "exec/ramblock.h" +#include "qemu/rcu.h" + +extern uint64_t total_dirty_pages; + +/** + * clear_bmap_size: calculate clear bitmap size + * + * @pages: number of guest pages + * @shift: guest page number shift + * + * Returns: number of bits for the clear bitmap + */ +static inline long clear_bmap_size(uint64_t pages, uint8_t shift) +{ + return DIV_ROUND_UP(pages, 1UL << shift); +} + +/** + * clear_bmap_set: set clear bitmap for the page range. Must be with + * bitmap_mutex held. + * + * @rb: the ramblock to operate on + * @start: the start page number + * @size: number of pages to set in the bitmap + * + * Returns: None + */ +static inline void clear_bmap_set(RAMBlock *rb, uint64_t start, + uint64_t npages) +{ + uint8_t shift =3D rb->clear_bmap_shift; + + bitmap_set(rb->clear_bmap, start >> shift, clear_bmap_size(npages, shi= ft)); +} + +/** + * clear_bmap_test_and_clear: test clear bitmap for the page, clear if set. + * Must be with bitmap_mutex held. + * + * @rb: the ramblock to operate on + * @page: the page number to check + * + * Returns: true if the bit was set, false otherwise + */ +static inline bool clear_bmap_test_and_clear(RAMBlock *rb, uint64_t page) +{ + uint8_t shift =3D rb->clear_bmap_shift; + + return bitmap_test_and_clear(rb->clear_bmap, page >> shift, 1); +} + +static inline bool offset_in_ramblock(RAMBlock *b, ram_addr_t offset) +{ + return (b && b->host && offset < b->used_length) ? true : false; +} + +static inline void *ramblock_ptr(RAMBlock *block, ram_addr_t offset) +{ + assert(offset_in_ramblock(block, offset)); + return (char *)block->host + offset; +} + +static inline unsigned long int ramblock_recv_bitmap_offset(void *host_add= r, + RAMBlock *rb) +{ + uint64_t host_addr_offset =3D + (uint64_t)(uintptr_t)(host_addr - (void *)rb->host); + return host_addr_offset >> TARGET_PAGE_BITS; +} + +/* Clear whole block of mem */ +static inline void qemu_ram_block_writeback(RAMBlock *block) +{ + qemu_ram_msync(block, 0, block->used_length); +} + +#define DIRTY_CLIENTS_ALL ((1 << DIRTY_MEMORY_NUM) - 1) +#define DIRTY_CLIENTS_NOCODE (DIRTY_CLIENTS_ALL & ~(1 << DIRTY_MEMORY_COD= E)) + +static inline bool cpu_physical_memory_get_dirty(ram_addr_t start, + ram_addr_t length, + unsigned client) +{ + DirtyMemoryBlocks *blocks; + unsigned long end, page; + unsigned long idx, offset, base; + bool dirty =3D false; + + assert(client < DIRTY_MEMORY_NUM); + + end =3D TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS; + page =3D start >> TARGET_PAGE_BITS; + + WITH_RCU_READ_LOCK_GUARD() { + blocks =3D qatomic_rcu_read(&ram_list.dirty_memory[client]); + + idx =3D page / DIRTY_MEMORY_BLOCK_SIZE; + offset =3D page % DIRTY_MEMORY_BLOCK_SIZE; + base =3D page - offset; + while (page < end) { + unsigned long next =3D MIN(end, base + DIRTY_MEMORY_BLOCK_SIZE= ); + unsigned long num =3D next - base; + unsigned long found =3D find_next_bit(blocks->blocks[idx], + num, offset); + if (found < num) { + dirty =3D true; + break; + } + + page =3D next; + idx++; + offset =3D 0; + base +=3D DIRTY_MEMORY_BLOCK_SIZE; + } + } + + return dirty; +} + +static inline bool cpu_physical_memory_all_dirty(ram_addr_t start, + ram_addr_t length, + unsigned client) +{ + DirtyMemoryBlocks *blocks; + unsigned long end, page; + unsigned long idx, offset, base; + bool dirty =3D true; + + assert(client < DIRTY_MEMORY_NUM); + + end =3D TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS; + page =3D start >> TARGET_PAGE_BITS; + + RCU_READ_LOCK_GUARD(); + + blocks =3D qatomic_rcu_read(&ram_list.dirty_memory[client]); + + idx =3D page / DIRTY_MEMORY_BLOCK_SIZE; + offset =3D page % DIRTY_MEMORY_BLOCK_SIZE; + base =3D page - offset; + while (page < end) { + unsigned long next =3D MIN(end, base + DIRTY_MEMORY_BLOCK_SIZE); + unsigned long num =3D next - base; + unsigned long found =3D find_next_zero_bit(blocks->blocks[idx], nu= m, offset); + if (found < num) { + dirty =3D false; + break; + } + + page =3D next; + idx++; + offset =3D 0; + base +=3D DIRTY_MEMORY_BLOCK_SIZE; + } + + return dirty; +} + +static inline bool cpu_physical_memory_get_dirty_flag(ram_addr_t addr, + unsigned client) +{ + return cpu_physical_memory_get_dirty(addr, 1, client); +} + +static inline bool cpu_physical_memory_is_clean(ram_addr_t addr) +{ + bool vga =3D cpu_physical_memory_get_dirty_flag(addr, DIRTY_MEMORY_VGA= ); + bool code =3D cpu_physical_memory_get_dirty_flag(addr, DIRTY_MEMORY_CO= DE); + bool migration =3D + cpu_physical_memory_get_dirty_flag(addr, DIRTY_MEMORY_MIGRATION); + return !(vga && code && migration); +} + +static inline uint8_t cpu_physical_memory_range_includes_clean(ram_addr_t = start, + ram_addr_t = length, + uint8_t mas= k) +{ + uint8_t ret =3D 0; + + if (mask & (1 << DIRTY_MEMORY_VGA) && + !cpu_physical_memory_all_dirty(start, length, DIRTY_MEMORY_VGA)) { + ret |=3D (1 << DIRTY_MEMORY_VGA); + } + if (mask & (1 << DIRTY_MEMORY_CODE) && + !cpu_physical_memory_all_dirty(start, length, DIRTY_MEMORY_CODE)) { + ret |=3D (1 << DIRTY_MEMORY_CODE); + } + if (mask & (1 << DIRTY_MEMORY_MIGRATION) && + !cpu_physical_memory_all_dirty(start, length, DIRTY_MEMORY_MIGRATI= ON)) { + ret |=3D (1 << DIRTY_MEMORY_MIGRATION); + } + return ret; +} + +static inline void cpu_physical_memory_set_dirty_flag(ram_addr_t addr, + unsigned client) +{ + unsigned long page, idx, offset; + DirtyMemoryBlocks *blocks; + + assert(client < DIRTY_MEMORY_NUM); + + page =3D addr >> TARGET_PAGE_BITS; + idx =3D page / DIRTY_MEMORY_BLOCK_SIZE; + offset =3D page % DIRTY_MEMORY_BLOCK_SIZE; + + RCU_READ_LOCK_GUARD(); + + blocks =3D qatomic_rcu_read(&ram_list.dirty_memory[client]); + + set_bit_atomic(offset, blocks->blocks[idx]); +} + +static inline void cpu_physical_memory_set_dirty_range(ram_addr_t start, + ram_addr_t length, + uint8_t mask) +{ + DirtyMemoryBlocks *blocks[DIRTY_MEMORY_NUM]; + unsigned long end, page; + unsigned long idx, offset, base; + int i; + + if (!mask && !xen_enabled()) { + return; + } + + end =3D TARGET_PAGE_ALIGN(start + length) >> TARGET_PAGE_BITS; + page =3D start >> TARGET_PAGE_BITS; + + WITH_RCU_READ_LOCK_GUARD() { + for (i =3D 0; i < DIRTY_MEMORY_NUM; i++) { + blocks[i] =3D qatomic_rcu_read(&ram_list.dirty_memory[i]); + } + + idx =3D page / DIRTY_MEMORY_BLOCK_SIZE; + offset =3D page % DIRTY_MEMORY_BLOCK_SIZE; + base =3D page - offset; + while (page < end) { + unsigned long next =3D MIN(end, base + DIRTY_MEMORY_BLOCK_SIZE= ); + + if (likely(mask & (1 << DIRTY_MEMORY_MIGRATION))) { + bitmap_set_atomic(blocks[DIRTY_MEMORY_MIGRATION]->blocks[i= dx], + offset, next - page); + } + if (unlikely(mask & (1 << DIRTY_MEMORY_VGA))) { + bitmap_set_atomic(blocks[DIRTY_MEMORY_VGA]->blocks[idx], + offset, next - page); + } + if (unlikely(mask & (1 << DIRTY_MEMORY_CODE))) { + bitmap_set_atomic(blocks[DIRTY_MEMORY_CODE]->blocks[idx], + offset, next - page); + } + + page =3D next; + idx++; + offset =3D 0; + base +=3D DIRTY_MEMORY_BLOCK_SIZE; + } + } + + xen_hvm_modified_memory(start, length); +} + +#if !defined(_WIN32) + +/* + * Contrary to cpu_physical_memory_sync_dirty_bitmap() this function retur= ns + * the number of dirty pages in @bitmap passed as argument. On the other h= and, + * cpu_physical_memory_sync_dirty_bitmap() returns newly dirtied pages that + * weren't set in the global migration bitmap. + */ +static inline +uint64_t cpu_physical_memory_set_dirty_lebitmap(unsigned long *bitmap, + ram_addr_t start, + ram_addr_t pages) +{ + unsigned long i, j; + unsigned long page_number, c, nbits; + hwaddr addr; + ram_addr_t ram_addr; + uint64_t num_dirty =3D 0; + unsigned long len =3D (pages + HOST_LONG_BITS - 1) / HOST_LONG_BITS; + unsigned long hpratio =3D qemu_real_host_page_size() / TARGET_PAGE_SIZ= E; + unsigned long page =3D BIT_WORD(start >> TARGET_PAGE_BITS); + + /* start address is aligned at the start of a word? */ + if ((((page * BITS_PER_LONG) << TARGET_PAGE_BITS) =3D=3D start) && + (hpratio =3D=3D 1)) { + unsigned long **blocks[DIRTY_MEMORY_NUM]; + unsigned long idx; + unsigned long offset; + long k; + long nr =3D BITS_TO_LONGS(pages); + + idx =3D (start >> TARGET_PAGE_BITS) / DIRTY_MEMORY_BLOCK_SIZE; + offset =3D BIT_WORD((start >> TARGET_PAGE_BITS) % + DIRTY_MEMORY_BLOCK_SIZE); + + WITH_RCU_READ_LOCK_GUARD() { + for (i =3D 0; i < DIRTY_MEMORY_NUM; i++) { + blocks[i] =3D + qatomic_rcu_read(&ram_list.dirty_memory[i])->blocks; + } + + for (k =3D 0; k < nr; k++) { + if (bitmap[k]) { + unsigned long temp =3D leul_to_cpu(bitmap[k]); + + nbits =3D ctpopl(temp); + qatomic_or(&blocks[DIRTY_MEMORY_VGA][idx][offset], tem= p); + + if (global_dirty_tracking) { + qatomic_or( + &blocks[DIRTY_MEMORY_MIGRATION][idx][offse= t], + temp); + if (unlikely( + global_dirty_tracking & GLOBAL_DIRTY_DIRTY_RAT= E)) { + total_dirty_pages +=3D nbits; + } + } + + num_dirty +=3D nbits; + + if (tcg_enabled()) { + qatomic_or(&blocks[DIRTY_MEMORY_CODE][idx][offset], + temp); + } + } + + if (++offset >=3D BITS_TO_LONGS(DIRTY_MEMORY_BLOCK_SIZE)) { + offset =3D 0; + idx++; + } + } + } + + xen_hvm_modified_memory(start, pages << TARGET_PAGE_BITS); + } else { + uint8_t clients =3D tcg_enabled() ? DIRTY_CLIENTS_ALL : DIRTY_CLIE= NTS_NOCODE; + + if (!global_dirty_tracking) { + clients &=3D ~(1 << DIRTY_MEMORY_MIGRATION); + } + + /* + * bitmap-traveling is faster than memory-traveling (for addr...) + * especially when most of the memory is not dirty. + */ + for (i =3D 0; i < len; i++) { + if (bitmap[i] !=3D 0) { + c =3D leul_to_cpu(bitmap[i]); + nbits =3D ctpopl(c); + if (unlikely(global_dirty_tracking & GLOBAL_DIRTY_DIRTY_RA= TE)) { + total_dirty_pages +=3D nbits; + } + num_dirty +=3D nbits; + do { + j =3D ctzl(c); + c &=3D ~(1ul << j); + page_number =3D (i * HOST_LONG_BITS + j) * hpratio; + addr =3D page_number * TARGET_PAGE_SIZE; + ram_addr =3D start + addr; + cpu_physical_memory_set_dirty_range(ram_addr, + TARGET_PAGE_SIZE * hpratio, clients= ); + } while (c !=3D 0); + } + } + } + + return num_dirty; +} +#endif /* not _WIN32 */ + +static inline void cpu_physical_memory_dirty_bits_cleared(ram_addr_t start, + ram_addr_t lengt= h) +{ + if (tcg_enabled()) { + tlb_reset_dirty_range_all(start, length); + } + +} +bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start, + ram_addr_t length, + unsigned client); + +DirtyBitmapSnapshot *cpu_physical_memory_snapshot_and_clear_dirty + (MemoryRegion *mr, hwaddr offset, hwaddr length, unsigned client); + +bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot *snap, + ram_addr_t start, + ram_addr_t length); + +static inline void cpu_physical_memory_clear_dirty_range(ram_addr_t start, + ram_addr_t length) +{ + cpu_physical_memory_test_and_clear_dirty(start, length, DIRTY_MEMORY_M= IGRATION); + cpu_physical_memory_test_and_clear_dirty(start, length, DIRTY_MEMORY_V= GA); + cpu_physical_memory_test_and_clear_dirty(start, length, DIRTY_MEMORY_C= ODE); +} + + +/* Called with RCU critical section */ +static inline +uint64_t cpu_physical_memory_sync_dirty_bitmap(RAMBlock *rb, + ram_addr_t start, + ram_addr_t length) +{ + ram_addr_t addr; + unsigned long word =3D BIT_WORD((start + rb->offset) >> TARGET_PAGE_BI= TS); + uint64_t num_dirty =3D 0; + unsigned long *dest =3D rb->bmap; + + /* start address and length is aligned at the start of a word? */ + if (((word * BITS_PER_LONG) << TARGET_PAGE_BITS) =3D=3D + (start + rb->offset) && + !(length & ((BITS_PER_LONG << TARGET_PAGE_BITS) - 1))) { + int k; + int nr =3D BITS_TO_LONGS(length >> TARGET_PAGE_BITS); + unsigned long * const *src; + unsigned long idx =3D (word * BITS_PER_LONG) / DIRTY_MEMORY_BLOCK_= SIZE; + unsigned long offset =3D BIT_WORD((word * BITS_PER_LONG) % + DIRTY_MEMORY_BLOCK_SIZE); + unsigned long page =3D BIT_WORD(start >> TARGET_PAGE_BITS); + + src =3D qatomic_rcu_read( + &ram_list.dirty_memory[DIRTY_MEMORY_MIGRATION])->blocks; + + for (k =3D page; k < page + nr; k++) { + if (src[idx][offset]) { + unsigned long bits =3D qatomic_xchg(&src[idx][offset], 0); + unsigned long new_dirty; + new_dirty =3D ~dest[k]; + dest[k] |=3D bits; + new_dirty &=3D bits; + num_dirty +=3D ctpopl(new_dirty); + } + + if (++offset >=3D BITS_TO_LONGS(DIRTY_MEMORY_BLOCK_SIZE)) { + offset =3D 0; + idx++; + } + } + if (num_dirty) { + cpu_physical_memory_dirty_bits_cleared(start, length); + } + + if (rb->clear_bmap) { + /* + * Postpone the dirty bitmap clear to the point before we + * really send the pages, also we will split the clear + * dirty procedure into smaller chunks. + */ + clear_bmap_set(rb, start >> TARGET_PAGE_BITS, + length >> TARGET_PAGE_BITS); + } else { + /* Slow path - still do that in a huge chunk */ + memory_region_clear_dirty_bitmap(rb->mr, start, length); + } + } else { + ram_addr_t offset =3D rb->offset; + + for (addr =3D 0; addr < length; addr +=3D TARGET_PAGE_SIZE) { + if (cpu_physical_memory_test_and_clear_dirty( + start + addr + offset, + TARGET_PAGE_SIZE, + DIRTY_MEMORY_MIGRATION)) { + long k =3D (start + addr) >> TARGET_PAGE_BITS; + if (!test_and_set_bit(k, dest)) { + num_dirty++; + } + } + } + } + + return num_dirty; +} + +#endif diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index 801cff16a5..a80547006b 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -35,6 +35,7 @@ #include "qemu/bswap.h" #include "exec/memory.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "qemu/event_notifier.h" #include "qemu/main-loop.h" #include "trace.h" diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index dba4831cd1..d4b381641c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -28,6 +28,7 @@ #include "exec/tb-flush.h" #include "exec/memory-internal.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "exec/mmu-access-type.h" #include "exec/tlb-common.h" #include "exec/vaddr.h" diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index fdf6d8ac19..48015be829 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -41,6 +41,7 @@ #endif #else #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #endif =20 #include "exec/cputlb.h" diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 5c02037c56..a9833530c7 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -75,6 +75,7 @@ #include "hw/virtio/vhost-scsi-common.h" =20 #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "exec/confidential-guest-support.h" #include "hw/usb.h" #include "qemu/config-file.h" diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index 2f74923560..5eef7475c1 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -28,6 +28,7 @@ #include "qapi/visitor.h" #include "sysemu/hw_accel.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "target/ppc/cpu.h" #include "target/ppc/mmu-hash64.h" #include "cpu-models.h" diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 7e24084673..a91fea1304 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -35,6 +35,7 @@ #include "hw/ppc/spapr.h" #include "hw/pci-host/spapr.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include #include "trace.h" #include "qemu/error-report.h" diff --git a/hw/remote/memory.c b/hw/remote/memory.c index 6d60da91e0..0af2a2f3fe 100644 --- a/hw/remote/memory.c +++ b/hw/remote/memory.c @@ -12,6 +12,7 @@ =20 #include "hw/remote/memory.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "qapi/error.h" =20 static void remote_sysmem_reset(void) diff --git a/hw/remote/proxy-memory-listener.c b/hw/remote/proxy-memory-lis= tener.c index a926f61ebe..3948751ed7 100644 --- a/hw/remote/proxy-memory-listener.c +++ b/hw/remote/proxy-memory-listener.c @@ -13,6 +13,7 @@ #include "exec/memory.h" #include "exec/cpu-common.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "hw/remote/mpqemu-link.h" diff --git a/hw/s390x/s390-stattrib-kvm.c b/hw/s390x/s390-stattrib-kvm.c index eeaa811098..b495d81296 100644 --- a/hw/s390x/s390-stattrib-kvm.c +++ b/hw/s390x/s390-stattrib-kvm.c @@ -16,6 +16,7 @@ #include "qemu/error-report.h" #include "sysemu/kvm.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "kvm/kvm_s390x.h" #include "qapi/error.h" =20 diff --git a/hw/s390x/s390-stattrib.c b/hw/s390x/s390-stattrib.c index c4259b5327..fe7945e856 100644 --- a/hw/s390x/s390-stattrib.c +++ b/hw/s390x/s390-stattrib.c @@ -17,6 +17,7 @@ #include "hw/s390x/storage-attributes.h" #include "qemu/error-report.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "qapi/error.h" #include "qapi/qmp/qdict.h" #include "cpu.h" diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index fe03f716f3..5b6fe1a18a 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -14,6 +14,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "exec/confidential-guest-support.h" #include "hw/boards.h" #include "hw/s390x/s390-virtio-hcall.h" diff --git a/hw/vfio/common.c b/hw/vfio/common.c index dcef44fe55..2e7a02cd4b 100644 --- a/hw/vfio/common.c +++ b/hw/vfio/common.c @@ -30,6 +30,7 @@ #include "exec/address-spaces.h" #include "exec/memory.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "hw/hw.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" diff --git a/hw/vfio/container.c b/hw/vfio/container.c index 9ccdb639ac..f0bc9e8c2b 100644 --- a/hw/vfio/container.c +++ b/hw/vfio/container.c @@ -26,6 +26,7 @@ #include "exec/address-spaces.h" #include "exec/memory.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "qemu/error-report.h" #include "qemu/range.h" #include "sysemu/reset.h" diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index e7bece4ea1..120c82f3de 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -26,6 +26,7 @@ #include "qemu/chardev_open.h" #include "pci.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" =20 static int iommufd_cdev_map(const VFIOContainerBase *bcontainer, hwaddr io= va, ram_addr_t size, void *vaddr, bool readonly) diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c index 01aa11013e..f5698eeae0 100644 --- a/hw/vfio/migration.c +++ b/hw/vfio/migration.c @@ -27,6 +27,7 @@ #include "qapi/qapi-events-vfio.h" #include "exec/ramlist.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "pci.h" #include "trace.h" #include "hw/hw.h" diff --git a/hw/vfio/spapr.c b/hw/vfio/spapr.c index 018bd20481..980147338a 100644 --- a/hw/vfio/spapr.c +++ b/hw/vfio/spapr.c @@ -20,6 +20,7 @@ #include "hw/vfio/vfio-common.h" #include "hw/hw.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "qemu/error-report.h" #include "qapi/error.h" #include "trace.h" diff --git a/hw/virtio/virtio-mem.c b/hw/virtio/virtio-mem.c index 80ada89551..dae94dbbde 100644 --- a/hw/virtio/virtio-mem.c +++ b/hw/virtio/virtio-mem.c @@ -25,6 +25,7 @@ #include "qapi/error.h" #include "qapi/visitor.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "migration/misc.h" #include "hw/boards.h" #include "hw/qdev-properties.h" diff --git a/migration/ram.c b/migration/ram.c index 05ff9eb328..82c44e8213 100644 --- a/migration/ram.c +++ b/migration/ram.c @@ -49,6 +49,7 @@ #include "qapi/qmp/qerror.h" #include "trace.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "exec/target_page.h" #include "qemu/rcu_queue.h" #include "migration/colo.h" diff --git a/plugins/api.c b/plugins/api.c index 24ea64e2de..77b55cff74 100644 --- a/plugins/api.c +++ b/plugins/api.c @@ -50,6 +50,7 @@ #include "qapi/error.h" #include "migration/blocker.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "qemu/plugin-memory.h" #include "hw/boards.h" #else diff --git a/system/memory.c b/system/memory.c index 85f6834cb3..7eae1bbda7 100644 --- a/system/memory.c +++ b/system/memory.c @@ -27,6 +27,7 @@ =20 #include "exec/memory-internal.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "sysemu/kvm.h" #include "sysemu/runstate.h" #include "sysemu/tcg.h" diff --git a/system/physmem.c b/system/physmem.c index 3f937a5e58..26cfb84454 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -67,6 +67,7 @@ =20 #include "exec/memory-internal.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" =20 #include "qemu/pmem.h" =20 diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index b017b26d07..0950a1c6f1 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -25,6 +25,7 @@ #include "exec/page-protection.h" #ifndef CONFIG_USER_ONLY #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #endif #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 3efc28f18b..f764931426 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -42,6 +42,7 @@ #include "gdbstub/enums.h" #include "exec/memattrs.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "sysemu/hostmem.h" #include "qemu/cutils.h" #include "qemu/main-loop.h" diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index 8ffe0159d8..c8045d873c 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -42,6 +42,7 @@ #include "sysemu/device_tree.h" #include "gdbstub/enums.h" #include "exec/ram_addr.h" +#include "sysemu/physmem-target.h" #include "trace.h" #include "hw/s390x/s390-pci-inst.h" #include "hw/s390x/s390-pci-bus.h" --=20 2.45.2 From nobody Sat Nov 23 17:19:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1731547148; cv=none; d=zohomail.com; s=zohoarc; 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2002:a05:600c:4fc5:b0:431:55f3:d34e with SMTP id 5b1f17b1804b1-432d9761bdcmr12005115e9.15.1731546969598; Wed, 13 Nov 2024 17:16:09 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Paolo Bonzini , Richard Henderson , Anton Johansson , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Thomas Huth , qemu-arm@nongnu.org, Peter Xu , Pierrick Bouvier , qemu-riscv@nongnu.org, David Hildenbrand , Peter Maydell , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-s390x@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 22/24] exec/cpu-common: Move ram_addr_t related methods to 'exec/ram_addr.h' Date: Thu, 14 Nov 2024 02:13:07 +0100 Message-ID: <20241114011310.3615-23-philmd@linaro.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241114011310.3615-1-philmd@linaro.org> References: <20241114011310.3615-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731547150115116600 Move methods related to the ram_addr_t type to the specific "exec/ram_addr.h" header. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- include/exec/cpu-common.h | 56 +------------------------------- include/exec/ram_addr.h | 56 ++++++++++++++++++++++++++++++++ include/exec/translation-block.h | 2 +- 3 files changed, 58 insertions(+), 56 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 638dc806a5..b790202c56 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -54,61 +54,7 @@ enum device_endian { #define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN #endif =20 -/* address in the RAM (different from a physical address) */ -#if defined(CONFIG_XEN_BACKEND) -typedef uint64_t ram_addr_t; -# define RAM_ADDR_MAX UINT64_MAX -# define RAM_ADDR_FMT "%" PRIx64 -#else -typedef uintptr_t ram_addr_t; -# define RAM_ADDR_MAX UINTPTR_MAX -# define RAM_ADDR_FMT "%" PRIxPTR -#endif - -/* memory API */ - -void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); -/* This should not be used by devices. */ -ram_addr_t qemu_ram_addr_from_host(void *ptr); -ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr); -RAMBlock *qemu_ram_block_by_name(const char *name); - -/* - * Translates a host ptr back to a RAMBlock and an offset in that RAMBlock. - * - * @ptr: The host pointer to translate. - * @round_offset: Whether to round the result offset down to a target page - * @offset: Will be set to the offset within the returned RAMBlock. - * - * Returns: RAMBlock (or NULL if not found) - * - * By the time this function returns, the returned pointer is not protected - * by RCU anymore. If the caller is not within an RCU critical section and - * does not hold the BQL, it must have other means of protecting the - * pointer, such as a reference to the memory region that owns the RAMBloc= k. - */ -RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, - ram_addr_t *offset); -ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host); -void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *de= v); -void qemu_ram_unset_idstr(RAMBlock *block); -const char *qemu_ram_get_idstr(RAMBlock *rb); -void *qemu_ram_get_host_addr(RAMBlock *rb); -ram_addr_t qemu_ram_get_offset(RAMBlock *rb); -ram_addr_t qemu_ram_get_used_length(RAMBlock *rb); -ram_addr_t qemu_ram_get_max_length(RAMBlock *rb); -bool qemu_ram_is_shared(RAMBlock *rb); -bool qemu_ram_is_noreserve(RAMBlock *rb); -bool qemu_ram_is_uf_zeroable(RAMBlock *rb); -void qemu_ram_set_uf_zeroable(RAMBlock *rb); -bool qemu_ram_is_migratable(RAMBlock *rb); -void qemu_ram_set_migratable(RAMBlock *rb); -void qemu_ram_unset_migratable(RAMBlock *rb); -bool qemu_ram_is_named_file(RAMBlock *rb); -int qemu_ram_get_fd(RAMBlock *rb); - -size_t qemu_ram_pagesize(RAMBlock *block); -size_t qemu_ram_pagesize_largest(void); +#include "exec/ram_addr.h" =20 /** * cpu_address_space_init: diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index 80f6dc7564..e0620ddb03 100644 --- a/include/exec/ram_addr.h +++ b/include/exec/ram_addr.h @@ -21,6 +21,62 @@ =20 #ifndef CONFIG_USER_ONLY =20 +/* address in the RAM (different from a physical address) */ +#if defined(CONFIG_XEN_BACKEND) +typedef uint64_t ram_addr_t; +# define RAM_ADDR_MAX UINT64_MAX +# define RAM_ADDR_FMT "%" PRIx64 +#else +typedef uintptr_t ram_addr_t; +# define RAM_ADDR_MAX UINTPTR_MAX +# define RAM_ADDR_FMT "%" PRIxPTR +#endif + +/* memory API */ + +void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); +/* This should not be used by devices. */ +ram_addr_t qemu_ram_addr_from_host(void *ptr); +ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr); +RAMBlock *qemu_ram_block_by_name(const char *name); + +/* + * Translates a host ptr back to a RAMBlock and an offset in that RAMBlock. + * + * @ptr: The host pointer to translate. + * @round_offset: Whether to round the result offset down to a target page + * @offset: Will be set to the offset within the returned RAMBlock. + * + * Returns: RAMBlock (or NULL if not found) + * + * By the time this function returns, the returned pointer is not protected + * by RCU anymore. If the caller is not within an RCU critical section and + * does not hold the BQL, it must have other means of protecting the + * pointer, such as a reference to the memory region that owns the RAMBloc= k. + */ +RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, + ram_addr_t *offset); +ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host); +void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *de= v); +void qemu_ram_unset_idstr(RAMBlock *block); +const char *qemu_ram_get_idstr(RAMBlock *rb); +void *qemu_ram_get_host_addr(RAMBlock *rb); +ram_addr_t qemu_ram_get_offset(RAMBlock *rb); +ram_addr_t qemu_ram_get_used_length(RAMBlock *rb); +ram_addr_t qemu_ram_get_max_length(RAMBlock *rb); +bool qemu_ram_is_shared(RAMBlock *rb); +bool qemu_ram_is_noreserve(RAMBlock *rb); +bool qemu_ram_is_uf_zeroable(RAMBlock *rb); +void qemu_ram_set_uf_zeroable(RAMBlock *rb); +bool qemu_ram_is_migratable(RAMBlock *rb); +void qemu_ram_set_migratable(RAMBlock *rb); +void qemu_ram_unset_migratable(RAMBlock *rb); +bool qemu_ram_is_named_file(RAMBlock *rb); +int qemu_ram_get_fd(RAMBlock *rb); + +size_t qemu_ram_pagesize(RAMBlock *block); +size_t qemu_ram_pagesize_largest(void); + bool ramblock_is_pmem(RAMBlock *rb); =20 long qemu_minrampagesize(void); diff --git a/include/exec/translation-block.h b/include/exec/translation-bl= ock.h index b99afb0077..9c4757882c 100644 --- a/include/exec/translation-block.h +++ b/include/exec/translation-block.h @@ -8,7 +8,7 @@ #define EXEC_TRANSLATION_BLOCK_H =20 #include "qemu/thread.h" -#include "exec/cpu-common.h" +#include "exec/ram_addr.h" #include "exec/vaddr.h" #ifdef CONFIG_USER_ONLY #include "qemu/interval-tree.h" --=20 2.45.2 From nobody Sat Nov 23 17:19:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731547208351116600 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- include/exec/memory.h | 2 +- include/exec/ram_addr.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/include/exec/memory.h b/include/exec/memory.h index 9458e2801d..58faa3eb08 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -28,6 +28,7 @@ #include "qemu/notify.h" #include "qom/object.h" #include "qemu/rcu.h" +#include "exec/ram_addr.h" =20 #define RAM_ADDR_INVALID (~(ram_addr_t)0) =20 @@ -2973,7 +2974,6 @@ MemTxResult flatview_read_continue(FlatView *fv, hwad= dr addr, MemTxAttrs attrs, void *buf, hwaddr len, hwaddr addr1, hwaddr l, MemoryRegion *mr); -void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr); =20 /* Internal functions, part of the implementation of address_space_read_ca= ched * and address_space_write_cached. */ diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h index e0620ddb03..c4f220ae93 100644 --- a/include/exec/ram_addr.h +++ b/include/exec/ram_addr.h @@ -73,6 +73,7 @@ void qemu_ram_set_migratable(RAMBlock *rb); void qemu_ram_unset_migratable(RAMBlock *rb); bool qemu_ram_is_named_file(RAMBlock *rb); int qemu_ram_get_fd(RAMBlock *rb); +void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr); =20 size_t qemu_ram_pagesize(RAMBlock *block); size_t qemu_ram_pagesize_largest(void); --=20 2.45.2 From nobody Sat Nov 23 17:19:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1731547248781116600 "ram_addr.h" contains declarations specific to system emulation, move it under the sysemu/ directory to clarify the API namespace. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson --- MAINTAINERS | 2 +- include/exec/cpu-common.h | 2 +- include/exec/memory.h | 2 +- include/exec/translation-block.h | 2 +- include/sysemu/physmem-target.h | 2 +- include/{exec =3D> sysemu}/ram_addr.h | 0 accel/kvm/kvm-all.c | 2 +- accel/tcg/cputlb.c | 2 +- accel/tcg/translate-all.c | 2 +- hw/ppc/spapr.c | 2 +- hw/ppc/spapr_caps.c | 2 +- hw/ppc/spapr_pci.c | 2 +- hw/remote/memory.c | 2 +- hw/remote/proxy-memory-listener.c | 2 +- hw/s390x/s390-stattrib-kvm.c | 2 +- hw/s390x/s390-stattrib.c | 2 +- hw/s390x/s390-virtio-ccw.c | 2 +- hw/vfio/common.c | 2 +- hw/vfio/container.c | 2 +- hw/vfio/iommufd.c | 2 +- hw/vfio/migration.c | 2 +- hw/vfio/spapr.c | 2 +- hw/virtio/virtio-mem.c | 2 +- migration/ram.c | 2 +- plugins/api.c | 2 +- system/memory.c | 2 +- system/physmem.c | 2 +- target/arm/tcg/mte_helper.c | 2 +- target/ppc/kvm.c | 2 +- target/s390x/kvm/kvm.c | 2 +- 30 files changed, 29 insertions(+), 29 deletions(-) rename include/{exec =3D> sysemu}/ram_addr.h (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 0027e56fa5..f303f73534 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3024,10 +3024,10 @@ S: Supported F: include/exec/ioport.h F: include/exec/memop.h F: include/exec/memory.h -F: include/exec/ram_addr.h F: include/exec/ramblock.h F: include/sysemu/memory_mapping.h F: include/sysemu/physmem-target.h +F: include/sysemu/ram_addr.h F: system/dma-helpers.c F: system/ioport.c F: system/memory.c diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index b790202c56..27f047b13b 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -54,7 +54,7 @@ enum device_endian { #define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN #endif =20 -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" =20 /** * cpu_address_space_init: diff --git a/include/exec/memory.h b/include/exec/memory.h index 58faa3eb08..b2e2d4590a 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -28,7 +28,7 @@ #include "qemu/notify.h" #include "qom/object.h" #include "qemu/rcu.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" =20 #define RAM_ADDR_INVALID (~(ram_addr_t)0) =20 diff --git a/include/exec/translation-block.h b/include/exec/translation-bl= ock.h index 9c4757882c..b72fcbbb18 100644 --- a/include/exec/translation-block.h +++ b/include/exec/translation-block.h @@ -8,7 +8,7 @@ #define EXEC_TRANSLATION_BLOCK_H =20 #include "qemu/thread.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "exec/vaddr.h" #ifdef CONFIG_USER_ONLY #include "qemu/interval-tree.h" diff --git a/include/sysemu/physmem-target.h b/include/sysemu/physmem-targe= t.h index b30c42da60..32efaf80b6 100644 --- a/include/sysemu/physmem-target.h +++ b/include/sysemu/physmem-target.h @@ -23,7 +23,7 @@ #include "sysemu/xen.h" #include "sysemu/tcg.h" #include "exec/cputlb.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "exec/ramlist.h" #include "exec/ramblock.h" #include "qemu/rcu.h" diff --git a/include/exec/ram_addr.h b/include/sysemu/ram_addr.h similarity index 100% rename from include/exec/ram_addr.h rename to include/sysemu/ram_addr.h diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index a80547006b..1ec73400a7 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -34,7 +34,7 @@ #include "sysemu/accel-blocker.h" #include "qemu/bswap.h" #include "exec/memory.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "qemu/event_notifier.h" #include "qemu/main-loop.h" diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d4b381641c..46f35ddd59 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -27,7 +27,7 @@ #include "exec/cputlb.h" #include "exec/tb-flush.h" #include "exec/memory-internal.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "exec/mmu-access-type.h" #include "exec/tlb-common.h" diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 48015be829..6d165fded6 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -40,7 +40,7 @@ #endif #endif #else -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #endif =20 diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index a9833530c7..ac9ab5986a 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -74,7 +74,7 @@ #include "hw/virtio/virtio-scsi.h" #include "hw/virtio/vhost-scsi-common.h" =20 -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "exec/confidential-guest-support.h" #include "hw/usb.h" diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c index 5eef7475c1..1d9ad3d6fc 100644 --- a/hw/ppc/spapr_caps.c +++ b/hw/ppc/spapr_caps.c @@ -27,7 +27,7 @@ #include "qapi/error.h" #include "qapi/visitor.h" #include "sysemu/hw_accel.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "target/ppc/cpu.h" #include "target/ppc/mmu-hash64.h" diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index a91fea1304..f6b2cb7396 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -34,7 +34,7 @@ #include "hw/pci/pci_host.h" #include "hw/ppc/spapr.h" #include "hw/pci-host/spapr.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include #include "trace.h" diff --git a/hw/remote/memory.c b/hw/remote/memory.c index 0af2a2f3fe..23df49099a 100644 --- a/hw/remote/memory.c +++ b/hw/remote/memory.c @@ -11,7 +11,7 @@ #include "qemu/osdep.h" =20 #include "hw/remote/memory.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "qapi/error.h" =20 diff --git a/hw/remote/proxy-memory-listener.c b/hw/remote/proxy-memory-lis= tener.c index 3948751ed7..0baf145016 100644 --- a/hw/remote/proxy-memory-listener.c +++ b/hw/remote/proxy-memory-listener.c @@ -12,7 +12,7 @@ #include "qemu/range.h" #include "exec/memory.h" #include "exec/cpu-common.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "qapi/error.h" #include "qemu/error-report.h" diff --git a/hw/s390x/s390-stattrib-kvm.c b/hw/s390x/s390-stattrib-kvm.c index b495d81296..48fd8e56cc 100644 --- a/hw/s390x/s390-stattrib-kvm.c +++ b/hw/s390x/s390-stattrib-kvm.c @@ -15,7 +15,7 @@ #include "hw/s390x/storage-attributes.h" #include "qemu/error-report.h" #include "sysemu/kvm.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "kvm/kvm_s390x.h" #include "qapi/error.h" diff --git a/hw/s390x/s390-stattrib.c b/hw/s390x/s390-stattrib.c index fe7945e856..5bad70ae5c 100644 --- a/hw/s390x/s390-stattrib.c +++ b/hw/s390x/s390-stattrib.c @@ -16,7 +16,7 @@ #include "hw/qdev-properties.h" #include "hw/s390x/storage-attributes.h" #include "qemu/error-report.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "qapi/error.h" #include "qapi/qmp/qdict.h" diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index 5b6fe1a18a..823a45cdec 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -13,7 +13,7 @@ =20 #include "qemu/osdep.h" #include "qapi/error.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "exec/confidential-guest-support.h" #include "hw/boards.h" diff --git a/hw/vfio/common.c b/hw/vfio/common.c index 2e7a02cd4b..01aae36194 100644 --- a/hw/vfio/common.c +++ b/hw/vfio/common.c @@ -29,7 +29,7 @@ #include "hw/vfio/pci.h" #include "exec/address-spaces.h" #include "exec/memory.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "hw/hw.h" #include "qemu/error-report.h" diff --git a/hw/vfio/container.c b/hw/vfio/container.c index f0bc9e8c2b..fe2254962b 100644 --- a/hw/vfio/container.c +++ b/hw/vfio/container.c @@ -25,7 +25,7 @@ #include "hw/vfio/vfio-common.h" #include "exec/address-spaces.h" #include "exec/memory.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "qemu/error-report.h" #include "qemu/range.h" diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index 120c82f3de..0b539cd55a 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -25,7 +25,7 @@ #include "qemu/cutils.h" #include "qemu/chardev_open.h" #include "pci.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" =20 static int iommufd_cdev_map(const VFIOContainerBase *bcontainer, hwaddr io= va, diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c index f5698eeae0..a057034e2a 100644 --- a/hw/vfio/migration.c +++ b/hw/vfio/migration.c @@ -26,7 +26,7 @@ #include "qapi/error.h" #include "qapi/qapi-events-vfio.h" #include "exec/ramlist.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "pci.h" #include "trace.h" diff --git a/hw/vfio/spapr.c b/hw/vfio/spapr.c index 980147338a..7b4159948f 100644 --- a/hw/vfio/spapr.c +++ b/hw/vfio/spapr.c @@ -19,7 +19,7 @@ =20 #include "hw/vfio/vfio-common.h" #include "hw/hw.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "qemu/error-report.h" #include "qapi/error.h" diff --git a/hw/virtio/virtio-mem.c b/hw/virtio/virtio-mem.c index dae94dbbde..1cccec24c3 100644 --- a/hw/virtio/virtio-mem.c +++ b/hw/virtio/virtio-mem.c @@ -24,7 +24,7 @@ #include "hw/virtio/virtio-mem.h" #include "qapi/error.h" #include "qapi/visitor.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "migration/misc.h" #include "hw/boards.h" diff --git a/migration/ram.c b/migration/ram.c index 82c44e8213..5da14601c1 100644 --- a/migration/ram.c +++ b/migration/ram.c @@ -48,7 +48,7 @@ #include "qapi/qapi-commands-migration.h" #include "qapi/qmp/qerror.h" #include "trace.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "exec/target_page.h" #include "qemu/rcu_queue.h" diff --git a/plugins/api.c b/plugins/api.c index 77b55cff74..24bf31804f 100644 --- a/plugins/api.c +++ b/plugins/api.c @@ -49,7 +49,7 @@ #ifndef CONFIG_USER_ONLY #include "qapi/error.h" #include "migration/blocker.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "qemu/plugin-memory.h" #include "hw/boards.h" diff --git a/system/memory.c b/system/memory.c index 7eae1bbda7..281f3c94e1 100644 --- a/system/memory.c +++ b/system/memory.c @@ -26,7 +26,7 @@ #include "trace.h" =20 #include "exec/memory-internal.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "sysemu/kvm.h" #include "sysemu/runstate.h" diff --git a/system/physmem.c b/system/physmem.c index 26cfb84454..d856c77d8b 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -66,7 +66,7 @@ #include "sysemu/replay.h" =20 #include "exec/memory-internal.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" =20 #include "qemu/pmem.h" diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 0950a1c6f1..c401a0981c 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -24,7 +24,7 @@ #include "exec/exec-all.h" #include "exec/page-protection.h" #ifndef CONFIG_USER_ONLY -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #endif #include "exec/cpu_ldst.h" diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index f764931426..f9dc722f3f 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -41,7 +41,7 @@ #include "trace.h" #include "gdbstub/enums.h" #include "exec/memattrs.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "sysemu/hostmem.h" #include "qemu/cutils.h" diff --git a/target/s390x/kvm/kvm.c b/target/s390x/kvm/kvm.c index c8045d873c..7dd4e403aa 100644 --- a/target/s390x/kvm/kvm.c +++ b/target/s390x/kvm/kvm.c @@ -41,7 +41,7 @@ #include "sysemu/runstate.h" #include "sysemu/device_tree.h" #include "gdbstub/enums.h" -#include "exec/ram_addr.h" +#include "sysemu/ram_addr.h" #include "sysemu/physmem-target.h" #include "trace.h" #include "hw/s390x/s390-pci-inst.h" --=20 2.45.2