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([187.101.65.72]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-724078a9063sm13392889b3a.75.2024.11.13.09.18.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Nov 2024 09:18:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1731518290; x=1732123090; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hxOZ1xHRmyOPMiXb0/ok1USMd7LW6yZMmDme9/JAjGU=; b=G33wVJdW/c/ZUP8X8Xa6Nsy2UDU/OAEqh3BQ93vPsodEhjfJGXc+NSX3KGP2rwxKtX JwptIwrRgcMuzJ2JMrO2qobLiYcz88E3Xb5SsjNspEkLCJtzts6Fd6cmP18Nr4GU3HmX sE5ERZ64HuXWCCJUz87AzdMl9WLMbWEqMffEqBNWnudSVPCt1aOH1RwJo7TeBeKCJnLj MwDWuMs0vRxQPaDLs7WYLNA9qk/IOrElFNoqObzNoyljBj654rOokwkR5gH5E7kQsHbo xyiMpFay+lRmvM7iUFVJhtzpRwYlWs+wW7vohgHTPDfp7Lmhh17Rfo1aU7m3BLHLeMnU TpLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731518290; x=1732123090; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hxOZ1xHRmyOPMiXb0/ok1USMd7LW6yZMmDme9/JAjGU=; b=ZGdyF5p6itVG6kEbpQTh+2RE0GGpjpguua6S6S6vg+LG6b4jH71L5cUOyobrbK3Y0Z rnd/i/RriPZVFQY5eRvZt1LvAZ6DNCsNW9mCwFSze1hPK43PLpEcmgYxKFeDPS0qZGyf WPqQikUbV2uZX3WpshQXZFP8Wc/uIwrB0ej36O7TUm3wyd/hjQbjoUz2c8sbVmY73VB7 p5Lc1CA5Gq6JzDm3fenWmGVbyIJ4bjI4mkzcZFD348vOIImgyjovuwRScdlbL/UJXzXd CQYdl/g/GxcHRZjoiHcfL6OpR9guci38Q7CLnPThuH+4QuwWSo7CpLli5cE3OFCFycJj Z7Iw== X-Gm-Message-State: AOJu0Yy8FQAhxRgwrEQ9CJiIqdL0IOE8kmu57KZABCJGdqH+i4eV008L m/hsiqfjPdgow1brF99FpuIpF6nIvEwjXmEb/vMy/KGHmAnb4ikfpYWi0WIA+Q+4xnaA8Gjec4O G X-Google-Smtp-Source: AGHT+IEeqllOGf9YcxQRsEgnC36t3oHcOCNhwh+pK1pzVtheB/iMShil1/IAOrcvAJ/gFJV/6cb8NQ== X-Received: by 2002:a05:6a00:3d55:b0:71e:695:41ee with SMTP id d2e1a72fcca58-72413278a86mr27996285b3a.5.1731518290187; Wed, 13 Nov 2024 09:18:10 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-10.0 2/9] target/riscv: add ssstateen Date: Wed, 13 Nov 2024 14:17:48 -0300 Message-ID: <20241113171755.978109-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241113171755.978109-1-dbarboza@ventanamicro.com> References: <20241113171755.978109-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=dbarboza@ventanamicro.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1731518343119116600 Content-Type: text/plain; charset="utf-8" ssstateen is defined in RVA22 as: "Supervisor-mode view of the state-enable extension. The supervisor-mode (sstateen0-3) and hypervisor-mode (hstateen0-3) state-enable registers must be provided." Add ssstateen as a named feature that is available if we also have smstateen. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg.h | 1 + target/riscv/tcg/tcg-cpu.c | 9 ++++++++- 3 files changed, 11 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f219f0c3b5..4ad91722a0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -191,6 +191,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), + ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), @@ -1607,6 +1608,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_e= xts[] =3D { */ const RISCVCPUMultiExtConfig riscv_cpu_named_features[] =3D { MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true), + MULTI_EXT_CFG_BOOL("ssstateen", ext_ssstateen, true), =20 DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 59d6fc445d..c7bf455614 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -139,6 +139,7 @@ struct RISCVCPUConfig { /* Named features */ bool ext_svade; bool ext_zic64b; + bool ext_ssstateen; =20 /* * Always 'true' booleans for named features diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index cd83968166..0b9be2b0d3 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -204,10 +204,15 @@ static void riscv_cpu_enable_named_feat(RISCVCPU *cpu= , uint32_t feat_offset) * All other named features are already enabled * in riscv_tcg_cpu_instance_init(). */ - if (feat_offset =3D=3D CPU_CFG_OFFSET(ext_zic64b)) { + switch (feat_offset) { + case CPU_CFG_OFFSET(ext_zic64b): cpu->cfg.cbom_blocksize =3D 64; cpu->cfg.cbop_blocksize =3D 64; cpu->cfg.cboz_blocksize =3D 64; + break; + case CPU_CFG_OFFSET(ext_ssstateen): + cpu->cfg.ext_smstateen =3D true; + break; } } =20 @@ -343,6 +348,8 @@ static void riscv_cpu_update_named_features(RISCVCPU *c= pu) cpu->cfg.ext_zic64b =3D cpu->cfg.cbom_blocksize =3D=3D 64 && cpu->cfg.cbop_blocksize =3D=3D 64 && cpu->cfg.cboz_blocksize =3D=3D 64; + + cpu->cfg.ext_ssstateen =3D cpu->cfg.ext_smstateen; } =20 static void riscv_cpu_validate_g(RISCVCPU *cpu) --=20 2.47.0