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Wed, 13 Nov 2024 03:05:22 -0800 (PST) From: Anton Blanchard To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Anton Blanchard , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: [PATCH v2] target/riscv: Add Tenstorrent Ascalon CPU Date: Wed, 13 Nov 2024 22:04:59 +1100 Message-Id: <20241113110459.1607299-1-antonb@tenstorrent.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::735; envelope-from=antonb@tenstorrent.com; helo=mail-qk1-x735.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @tenstorrent.com) X-ZM-MESSAGEID: 1731495974831116600 Content-Type: text/plain; charset="utf-8" Add a CPU entry for the Tenstorrent Ascalon CPU, a series of 2 wide to 8 wide RV64 cores. More details can be found at https://tenstorrent.com/ip/tt-ascalon Signed-off-by: Anton Blanchard Acked-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu-qom.h | 1 + target/riscv/cpu.c | 67 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 68 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 62115375cd..6547642287 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -49,6 +49,7 @@ #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") #define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1") +#define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME("tt-ascalon") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") =20 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f219f0c3b5..8447ad0dfb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -579,6 +579,72 @@ static void rv64_veyron_v1_cpu_init(Object *obj) #endif } =20 +/* Tenstorrent Ascalon */ +static void rv64_tt_ascalon_cpu_init(Object *obj) +{ + CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + + riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH | RVV); + env->priv_ver =3D PRIV_VERSION_1_13_0; + + /* Enable ISA extensions */ + cpu->cfg.mmu =3D true; + cpu->cfg.vlenb =3D 256 >> 3; + cpu->cfg.elen =3D 64; + cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; + cpu->cfg.rvv_ma_all_1s =3D true; + cpu->cfg.rvv_ta_all_1s =3D true; + cpu->cfg.misa_w =3D true; + cpu->cfg.pmp =3D true; + cpu->cfg.cbom_blocksize =3D 64; + cpu->cfg.cbop_blocksize =3D 64; + cpu->cfg.cboz_blocksize =3D 64; + cpu->cfg.ext_zic64b =3D true; + cpu->cfg.ext_zicbom =3D true; + cpu->cfg.ext_zicbop =3D true; + cpu->cfg.ext_zicboz =3D true; + cpu->cfg.ext_zicntr =3D true; + cpu->cfg.ext_zicond =3D true; + cpu->cfg.ext_zicsr =3D true; + cpu->cfg.ext_zifencei =3D true; + cpu->cfg.ext_zihintntl =3D true; + cpu->cfg.ext_zihintpause =3D true; + cpu->cfg.ext_zihpm =3D true; + cpu->cfg.ext_zimop =3D true; + cpu->cfg.ext_zawrs =3D true; + cpu->cfg.ext_zfa =3D true; + cpu->cfg.ext_zfbfmin =3D true; + cpu->cfg.ext_zfh =3D true; + cpu->cfg.ext_zfhmin =3D true; + cpu->cfg.ext_zcb =3D true; + cpu->cfg.ext_zcmop =3D true; + cpu->cfg.ext_zba =3D true; + cpu->cfg.ext_zbb =3D true; + cpu->cfg.ext_zbs =3D true; + cpu->cfg.ext_zkt =3D true; + cpu->cfg.ext_zvbb =3D true; + cpu->cfg.ext_zvbc =3D true; + cpu->cfg.ext_zvfbfmin =3D true; + cpu->cfg.ext_zvfbfwma =3D true; + cpu->cfg.ext_zvfh =3D true; + cpu->cfg.ext_zvfhmin =3D true; + cpu->cfg.ext_zvkng =3D true; + cpu->cfg.ext_smaia =3D true; + cpu->cfg.ext_smstateen =3D true; + cpu->cfg.ext_ssaia =3D true; + cpu->cfg.ext_sscofpmf =3D true; + cpu->cfg.ext_sstc =3D true; + cpu->cfg.ext_svade =3D true; + cpu->cfg.ext_svinval =3D true; + cpu->cfg.ext_svnapot =3D true; + cpu->cfg.ext_svpbmt =3D true; + +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(cpu, VM_1_10_SV57); +#endif +} + #ifdef CONFIG_TCG static void rv128_base_cpu_init(Object *obj) { @@ -2982,6 +3048,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_= cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_= cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c90= 6_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64, rv64_tt_ascalo= n_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1= _cpu_init), #ifdef CONFIG_TCG DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu= _init), --=20 2.34.1