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([193.104.68.137]) by smtp.googlemail.com with ESMTPSA id 4fb4d7f45d1cf-5cf03c8130dsm6137004a12.88.2024.11.12.08.42.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Nov 2024 08:42:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1731429748; x=1732034548; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Vgup44yY9AzwZEVS1bUWUEFU3T5oYiAM4TzncaEuWhY=; b=KO9dqpuWlRvL1/Z32AzVagNn5Jma3G39o1HnM73kWREs6Z1FelkRFI6Ep3bSjtivtK ccLQByFssLsJh4GMlAPHM6AvWJqzOMaU4Ayml39WMwBWk8Kz2F6z8kRJQCSgV03Xz07A 6XhfeJ+w8yxDlWPrQCEtz//RS6Hz+BhvSEL9YmQDUK3G/0B7ovDfUwrkHT9BGpnUMgKd A01cwJbk4AYSq2WFbZWoYOCjhNO6Sfvibwm+c3g6ZjSg4n6vycIM3vOOVonJLAVnTzrQ Sye9LchpZD6zYMnYu+sxDZ+4DNYyrpASOeSnZNv9az7MoaOuLOv+xR6WhrlWzspL19N3 9KHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731429748; x=1732034548; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Vgup44yY9AzwZEVS1bUWUEFU3T5oYiAM4TzncaEuWhY=; b=NLxacTOJOGAALgkDKv2LXc8ebiRPbZTK+kjBFg1rp5EGXc0SIVybUTMf16ddzKOBO/ DFdLR/VnrowXoNFP4+rceUeKRvK1YOOm2azPXxUmBbPuT2RS/HYIVnCUHWBkNj0xdH9V YTaQLfX70rXNyEWfnDFvuhLdCb+mhGXHSLb/xFbuHOwSWDNRwwdu+UuIg8nhp6/9YNgK ETQdY1TxNie7kFlos+S3JkqJIHuH/vLACwNKERatHxMjKho0TpZABUxXkORN20bAL1Gn qftqzcjGAefxNdM0+Fr2UZSqDw8oU70rUUCvmbvyISCYuxWLYDlLySKSGW2i5/wd7+pS SAkQ== X-Gm-Message-State: AOJu0YxLNb19dwW+EDKP5W+UU9QpP+bsaeEg4HU8TMYfhn/KXux7DnJP RYAExWk3cSt9RCYvJ+P1kGp08PzHla18PlpoBQUWBGLNPu0ELSPwigMD/TC+ X-Google-Smtp-Source: AGHT+IHhX+C/lp1sAo0GZbwBR0i23l0Jcn66J0OZJfXehj8od43wXyo0aKSbyX/QAJ7at2NrQvb2eg== X-Received: by 2002:a05:6402:5213:b0:5ce:fa24:fbaf with SMTP id 4fb4d7f45d1cf-5cf0a45c722mr5456318a12.9.1731429747584; Tue, 12 Nov 2024 08:42:27 -0800 (PST) From: Aleksandar Rakic X-Google-Original-From: Aleksandar Rakic To: qemu-devel@nongnu.org Cc: aleksandar.rakic@htecgroup.com, djordje.todorovic@htecgroup.com, cfu@mips.com, arikalo@gmail.com, peter.maydell@linaro.org, philmd@linaro.org, aurelien@aurel32.net, jiaxun.yang@flygoat.com, kwolf@redhat.com, hreitz@redhat.com, pbonzini@redhat.com, alex.bennee@linaro.org, pierrick.bouvier@linaro.org, berrange@redhat.com, Yongbok Kim , Aleksandar Markovic Subject: [PATCH v3 1/4] Add support for emulation of CRC32 instructions Date: Tue, 12 Nov 2024 17:41:27 +0100 Message-Id: <20241112164130.2396737-3-aleksandar.rakic@htecgroup.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241112164130.2396737-1-aleksandar.rakic@htecgroup.com> References: <20241112164130.2396737-1-aleksandar.rakic@htecgroup.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=rakicaleksandar1999@gmail.com; helo=mail-ed1-x531.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 12 Nov 2024 12:37:38 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1731433183398116600 Content-Type: text/plain; charset="utf-8" Add emulation of MIPS' CRC32 (Cyclic Redundancy Check) instructions. Reuse zlib crc32() and Linux crc32c(). Cherry-picked 4cc974938aee1588f852590509004e340c072940 from https://github.com/MIPS/gnutools-qemu Signed-off-by: Yongbok Kim Signed-off-by: Aleksandar Markovic Signed-off-by: Aleksandar Rakic Reviewed-by: Aleksandar Rikalo --- target/mips/helper.h | 2 ++ target/mips/meson.build | 1 + target/mips/tcg/op_helper.c | 26 ++++++++++++++++++++++++++ target/mips/tcg/rel6.decode | 5 +++++ target/mips/tcg/rel6_translate.c | 14 ++++++++++++++ target/mips/tcg/translate.c | 25 +++++++++++++++++++++++++ target/mips/tcg/translate.h | 3 +++ 7 files changed, 76 insertions(+) diff --git a/target/mips/helper.h b/target/mips/helper.h index 0f8462febb..752748d5e6 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -21,6 +21,8 @@ DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl) #endif =20 +DEF_HELPER_3(crc32, tl, tl, tl, i32) +DEF_HELPER_3(crc32c, tl, tl, tl, i32) DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32) =20 /* microMIPS functions */ diff --git a/target/mips/meson.build b/target/mips/meson.build index a26d1e1f79..d2d686fc0c 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -7,6 +7,7 @@ mips_ss.add(files( 'gdbstub.c', 'msa.c', )) +mips_ss.add(zlib) =20 if have_system subdir('sysemu') diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c index 65403f1a87..22600697f0 100644 --- a/target/mips/tcg/op_helper.c +++ b/target/mips/tcg/op_helper.c @@ -25,6 +25,8 @@ #include "exec/exec-all.h" #include "exec/memop.h" #include "fpu_helper.h" +#include "qemu/crc32c.h" +#include =20 static inline target_ulong bitswap(target_ulong v) { @@ -143,6 +145,30 @@ target_ulong helper_rotx(target_ulong rs, uint32_t shi= ft, uint32_t shiftx, return (int64_t)(int32_t)(uint32_t)tmp5; } =20 +/* these crc32 functions are based on target/arm/helper-a64.c */ +target_ulong helper_crc32(target_ulong val, target_ulong m, uint32_t sz) +{ + uint8_t buf[8]; + target_ulong mask =3D ((sz * 8) =3D=3D 64) ? + (target_ulong) -1ULL : + ((1ULL << (sz * 8)) - 1); + + m &=3D mask; + stq_le_p(buf, m); + return (int32_t) (crc32(val ^ 0xffffffff, buf, sz) ^ 0xffffffff); +} + +target_ulong helper_crc32c(target_ulong val, target_ulong m, uint32_t sz) +{ + uint8_t buf[8]; + target_ulong mask =3D ((sz * 8) =3D=3D 64) ? + (target_ulong) -1ULL : + ((1ULL << (sz * 8)) - 1); + m &=3D mask; + stq_le_p(buf, m); + return (int32_t) (crc32c(val, buf, sz) ^ 0xffffffff); +} + void helper_fork(target_ulong arg1, target_ulong arg2) { /* diff --git a/target/mips/tcg/rel6.decode b/target/mips/tcg/rel6.decode index d6989cf56e..5074338aa5 100644 --- a/target/mips/tcg/rel6.decode +++ b/target/mips/tcg/rel6.decode @@ -16,11 +16,16 @@ =20 &r rs rt rd sa =20 +&special3_crc rs rt c sz + @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r +@crc32 ...... rs:5 rt:5 ..... c:3 sz:2 ...... &special3_crc =20 LSA 000000 ..... ..... ..... 000 .. 000101 @lsa DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa =20 +CRC32 011111 ..... ..... 00000 ... .. 001111 @crc32 + REMOVED 010011 ----- ----- ----- ----- ------ # COP1X (COP3) =20 REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2 diff --git a/target/mips/tcg/rel6_translate.c b/target/mips/tcg/rel6_transl= ate.c index 59f237ba3b..423b323ba7 100644 --- a/target/mips/tcg/rel6_translate.c +++ b/target/mips/tcg/rel6_translate.c @@ -33,3 +33,17 @@ static bool trans_DLSA(DisasContext *ctx, arg_r *a) } return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa); } + +static bool trans_CRC32(DisasContext *ctx, arg_special3_crc *a) +{ + if (unlikely(!ctx->crcp) || + unlikely((a->sz =3D=3D 3) && + (!(ctx->hflags & MIPS_HFLAG_64))) || + unlikely((a->c >=3D 2))) { + gen_reserved_instruction(ctx); + return true; + } + gen_crc32(ctx, a->rt, a->rs, a->rt, + a->sz, a->c); + return true; +} diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index de7045874d..c97d1d37bd 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -13448,6 +13448,30 @@ static void decode_opc_special2_legacy(CPUMIPSStat= e *env, DisasContext *ctx) } } =20 +void gen_crc32(DisasContext *ctx, int rd, int rs, int rt, int sz, + int crc32c) +{ + TCGv t0; + TCGv t1; + TCGv_i32 tsz =3D tcg_constant_i32(1 << sz); + if (rd =3D=3D 0) { + /* Treat as NOP. */ + return; + } + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + + gen_load_gpr(t0, rt); + gen_load_gpr(t1, rs); + + if (crc32c) { + gen_helper_crc32c(cpu_gpr[rd], t0, t1, tsz); + } else { + gen_helper_crc32(cpu_gpr[rd], t0, t1, tsz); + } + +} + static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx) { int rs, rt, rd, sa; @@ -15094,6 +15118,7 @@ static void mips_tr_init_disas_context(DisasContext= Base *dcbase, CPUState *cs) ctx->abs2008 =3D (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; ctx->mi =3D (env->CP0_Config5 >> CP0C5_MI) & 1; ctx->gi =3D (env->CP0_Config5 >> CP0C5_GI) & 3; + ctx->crcp =3D (env->CP0_Config5 >> CP0C5_CRCP) & 1; restore_cpu_state(env, ctx); #ifdef CONFIG_USER_ONLY ctx->mem_idx =3D MIPS_HFLAG_UM; diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 1bf153d183..cb27ae78ae 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -51,6 +51,7 @@ typedef struct DisasContext { bool abs2008; bool mi; int gi; + bool crcp; } DisasContext; =20 #define DISAS_STOP DISAS_TARGET_0 @@ -181,6 +182,8 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs,= int sa); bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa); =20 void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel); +void gen_crc32(DisasContext *ctx, int rd, int rs, int rt, int sz, + int crc32c); =20 extern TCGv cpu_gpr[32], cpu_PC; #if defined(TARGET_MIPS64) --=20 2.34.1