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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2e99a4f6c96sm13495347a91.2.2024.11.12.01.12.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Nov 2024 01:12:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1731402730; x=1732007530; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ta9zlJxceH6xvI0lTGE/GAG3tOR+/5oYHysvex7gkPA=; b=MNxk4F2sYqAUGV/7tdIYEfAl8Mm3QZMJEIjVSWg3UB2pDJyVwyqrMXJudc4CytwyHd EQD1NnK9L/WT+o0VPOtBLjXzI6ifLb0XTIe1RoQSczaB75At+GKZLIuZUXfnJ6WVkb6K ZTNat1b20M8QM9xd4RWviWNu2kQe2AUzM3I9QkAqHqqa7CaCYWsw7xSugINJ5ImVkOAz Logveqlak7nle9B28C0Z4dWoBnG8dee6HjTmvf0Jpu62Svhz4FJTA9OW3DHl4MwfLsme M0/ZAWgzjDnlNDNQSnSFaVd0aiqnUbgZ3WUo9LYf2RafopAdcx4NFoJHSdmRl0+B4XJ5 kVCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1731402730; x=1732007530; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ta9zlJxceH6xvI0lTGE/GAG3tOR+/5oYHysvex7gkPA=; b=ZUEcpwGQbjRnnVy9STr8qlDoYOmgbt8ZtKZ2nJHVKIGYSqEHysop6AUVyrHViu+HIS UDW4VBVedRykNS03/9vXN7yd5GnK1Bdh52Gr3Yea6PczunuoEwuR5ZU7JhnuwX8+eUJG B6yfSfN/xHdb2s9iqIdMikqQo8u1MNHkCVYCBoLapXrzgECEHqyrGJ3oyodPuk4ZRaUA IqiP3uNn6GptnAEOAB7D1yA5v4FznV+xIHvBXPRFPEWP8nejfgHf4CO0oNvsutc+dbt6 15MxvUqOFTnhYdRVSHztszclU2gWCFkcnYXmIYoIApis02FxifrEytNjyw7wQroLzYUQ NVSg== X-Gm-Message-State: AOJu0Yy6/LYTiPuFuz6kFVnP1+wC+EPWUNT72JTOBYL42jVIdqIF6U5R dRg9kpEXaG8F44vLbkQ++8B9TaG9TYBpvvNhxP44vjUCY8hd+k5YL4P8rNn345NqkhVts6nE+QN IhGa8IEAaRkpjWPwdQhi1Nwzdnp28B6Wy/Ehl0z5qlc/vU0UjdVR4xc2UeJNDHRk6wMnYIZWX5X wqX8v87Pr5+igmSAXalUALm0hnHRcmF/M99Rk= X-Google-Smtp-Source: AGHT+IGG6YUoo8cyGL2W+pkYbQX+8vHpSZ5U0MkHdyeX1Fb1XCMofv8St8FOawzptzLBPVC6scLKPw== X-Received: by 2002:a17:90b:3d09:b0:2da:8e9b:f37b with SMTP id 98e67ed59e1d1-2e9b172af1fmr19875487a91.24.1731402729920; Tue, 12 Nov 2024 01:12:09 -0800 (PST) From: "Fea.Wang" To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "Fea.Wang" , Frank Chang , Jim Shu Subject: [PATCH v3 3/5] target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled Date: Tue, 12 Nov 2024 17:14:21 +0800 Message-Id: <20241112091423.2529583-4-fea.wang@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241112091423.2529583-1-fea.wang@sifive.com> References: <20241112091423.2529583-1-fea.wang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=fea.wang@sifive.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1731402847862116600 Content-Type: text/plain; charset="utf-8" Svukte extension add HUKTE bit, bit[24] in hstatus CSR. The written value will be masked when the svukte extension is not enabled. When hstatus[HUKTE] bit is set, HLV/HLVX/HSV work in the U-mode should do svukte check. Signed-off-by: Fea.Wang Reviewed-by: Frank Chang Reviewed-by: Jim Shu Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 4b9f899217..fe4e34c64a 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -604,6 +604,7 @@ typedef enum { #define HSTATUS_VTVM 0x00100000 #define HSTATUS_VTW 0x00200000 #define HSTATUS_VTSR 0x00400000 +#define HSTATUS_HUKTE 0x01000000 #define HSTATUS_VSXL 0x300000000 =20 #define HSTATUS32_WPRI 0xFF8FF87E diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 1936a6f32a..b6fa8ae53f 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3540,6 +3540,9 @@ static RISCVException read_hstatus(CPURISCVState *env= , int csrno, static RISCVException write_hstatus(CPURISCVState *env, int csrno, target_ulong val) { + if (!env_archcpu(env)->cfg.ext_svukte) { + val =3D val & (~HSTATUS_HUKTE); + } env->hstatus =3D val; if (riscv_cpu_mxl(env) !=3D MXL_RV32 && get_field(val, HSTATUS_VSXL) != =3D 2) { qemu_log_mask(LOG_UNIMP, --=20 2.34.1