From nobody Sat Nov 23 21:04:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 173137793548184.77749865544376; Mon, 11 Nov 2024 18:18:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tAgTh-0007BJ-Gz; Mon, 11 Nov 2024 21:18:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1tAgTc-0007AN-Ob for qemu-devel@nongnu.org; Mon, 11 Nov 2024 21:17:56 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1tAgTa-00046T-I3 for qemu-devel@nongnu.org; Mon, 11 Nov 2024 21:17:56 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxEK_OujJnNLg7AA--.13555S3; Tue, 12 Nov 2024 10:17:50 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMCx98DCujJniixSAA--.12416S6; Tue, 12 Nov 2024 10:17:50 +0800 (CST) From: Bibo Mao To: Song Gao , Paolo Bonzini , Zhao Liu , Igor Mammedov Cc: Jiaxun Yang , Xianglai Li , qemu-devel@nongnu.org Subject: [PATCH v4 4/6] hw/loongarch/virt: Init interrupt pin of CPU during plug interface Date: Tue, 12 Nov 2024 10:17:36 +0800 Message-Id: <20241112021738.1952851-5-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20241112021738.1952851-1-maobibo@loongson.cn> References: <20241112021738.1952851-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMCx98DCujJniixSAA--.12416S6 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1731377937951116600 Content-Type: text/plain; charset="utf-8" Move CPU object creation after interrupt controller ipi and extioi, and init interrupt pin of CPU in plug interface virt_cpu_plug(). So interrupt pin initialization of the cold-plug CPUs is the same with that of hot-plug CPUs. Signed-off-by: Bibo Mao --- hw/loongarch/virt.c | 84 ++++++++++++++++++++++++--------------------- 1 file changed, 45 insertions(+), 39 deletions(-) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 621380e2b3..0e0c6c202b 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -831,8 +831,7 @@ static void virt_irq_init(LoongArchVirtMachineState *lv= ms) DeviceState *pch_pic, *pch_msi; DeviceState *ipi, *extioi; SysBusDevice *d; - CPUState *cpu_state; - int cpu, i, start, num; + int i, start, num; uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle, pch_msi_ph= andle; =20 /* @@ -909,12 +908,6 @@ static void virt_irq_init(LoongArchVirtMachineState *l= vms) sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 1)); } =20 - /* Connect irq to cpu, including ipi and extioi irqchip */ - for (cpu =3D 0; cpu < ms->smp.cpus; cpu++) { - cpu_state =3D virt_get_cpu(ms, cpu); - virt_init_cpu_irq(ms, cpu_state); - } - /* Add Extend I/O Interrupt Controller node */ fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle); =20 @@ -960,6 +953,44 @@ static void virt_irq_init(LoongArchVirtMachineState *l= vms) virt_devices_init(pch_pic, lvms, &pch_pic_phandle, &pch_msi_phandle); } =20 +static void virt_init_cpus(MachineState *machine) +{ + int i; + MachineClass *mc =3D MACHINE_GET_CLASS(machine); + Object *cpuobj; + CPUState *cpu; + LoongArchCPU *lacpu; + LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(machine); + + /* Init CPUs */ + mc->possible_cpu_arch_ids(machine); + for (i =3D 0; i < machine->smp.cpus; i++) { + cpuobj =3D object_new(machine->cpu_type); + if (cpuobj =3D=3D NULL) { + error_report("Fail to create object with type %s ", + machine->cpu_type); + exit(EXIT_FAILURE); + } + + cpu =3D CPU(cpuobj); + cpu->cpu_index =3D i; + lacpu =3D LOONGARCH_CPU(cpuobj); + lacpu->phy_id =3D machine->possible_cpus->cpus[i].arch_id; + object_property_set_int(cpuobj, "socket-id", + machine->possible_cpus->cpus[i].props.sock= et_id, + NULL); + object_property_set_int(cpuobj, "core-id", + machine->possible_cpus->cpus[i].props.core= _id, + NULL); + object_property_set_int(cpuobj, "thread-id", + machine->possible_cpus->cpus[i].props.thre= ad_id, + NULL); + qdev_realize_and_unref(DEVICE(cpuobj), NULL, &error_fatal); + } + + fdt_add_cpu_nodes(lvms); +} + static void virt_firmware_init(LoongArchVirtMachineState *lvms) { char *filename =3D MACHINE(lvms)->firmware; @@ -1161,15 +1192,10 @@ static void fw_cfg_add_memory(MachineState *ms) =20 static void virt_init(MachineState *machine) { - LoongArchCPU *lacpu; const char *cpu_model =3D machine->cpu_type; MemoryRegion *address_space_mem =3D get_system_memory(); LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(machine); - int i; hwaddr base, size, ram_size =3D machine->ram_size; - MachineClass *mc =3D MACHINE_GET_CLASS(machine); - CPUState *cpu; - Object *cpuobj; =20 if (!cpu_model) { cpu_model =3D LOONGARCH_CPU_TYPE_NAME("la464"); @@ -1186,32 +1212,6 @@ static void virt_init(MachineState *machine) machine, "iocsr_misc", 0x428); memory_region_add_subregion(&lvms->system_iocsr, 0, &lvms->iocsr_mem); =20 - /* Init CPUs */ - mc->possible_cpu_arch_ids(machine); - for (i =3D 0; i < machine->smp.cpus; i++) { - cpuobj =3D object_new(machine->cpu_type); - if (cpuobj =3D=3D NULL) { - error_report("Fail to create object with type %s ", - machine->cpu_type); - exit(EXIT_FAILURE); - } - - cpu =3D CPU(cpuobj); - cpu->cpu_index =3D i; - lacpu =3D LOONGARCH_CPU(cpuobj); - lacpu->phy_id =3D machine->possible_cpus->cpus[i].arch_id; - object_property_set_int(cpuobj, "socket-id", - machine->possible_cpus->cpus[i].props.sock= et_id, - NULL); - object_property_set_int(cpuobj, "core-id", - machine->possible_cpus->cpus[i].props.core= _id, - NULL); - object_property_set_int(cpuobj, "thread-id", - machine->possible_cpus->cpus[i].props.thre= ad_id, - NULL); - qdev_realize_and_unref(DEVICE(cpuobj), NULL, &error_fatal); - } - fdt_add_cpu_nodes(lvms); fdt_add_memory_nodes(machine); fw_cfg_add_memory(machine); =20 @@ -1269,6 +1269,9 @@ static void virt_init(MachineState *machine) =20 /* Initialize the IO interrupt subsystem */ virt_irq_init(lvms); + + /* Init CPUs */ + virt_init_cpus(machine); platform_bus_add_all_fdt_nodes(machine->fdt, "/platic", VIRT_PLATFORM_BUS_BASEADDRESS, VIRT_PLATFORM_BUS_SIZE, @@ -1465,8 +1468,11 @@ static void virt_cpu_plug(HotplugHandler *hotplug_de= v, { CPUArchId *cpu_slot; LoongArchCPU *cpu =3D LOONGARCH_CPU(dev); + MachineState *ms =3D MACHINE(hotplug_dev); LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(hotplug_dev= ); =20 + /* Connect irq to cpu, including ipi and extioi irqchip */ + virt_init_cpu_irq(ms, CPU(cpu)); cpu_slot =3D virt_find_cpu_slot(MACHINE(lvms), cpu->phy_id); cpu_slot->cpu =3D CPU(dev); return; --=20 2.39.3