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Mon, 11 Nov 2024 05:03:30 -0800 (PST) From: Paolo Savini To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Paolo Savini , Richard Handerson , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Helene Chelin , Nathan Egge , Max Chou Subject: [RFC v5 1/1] target/riscv: rvv: reduce the overhead for simple RISC-V vector unit-stride loads and stores Date: Mon, 11 Nov 2024 13:03:24 +0000 Message-ID: <20241111130324.32487-2-paolo.savini@embecosm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241111130324.32487-1-paolo.savini@embecosm.com> References: <20241111130324.32487-1-paolo.savini@embecosm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=paolo.savini@embecosm.com; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @embecosm.com) X-ZM-MESSAGEID: 1731330268779116600 Content-Type: text/plain; charset="utf-8" This patch improves the performance of the emulation of the RVV unit-stride loads and stores in the following cases: - when the data being loaded/stored per iteration amounts to 8 bytes or les= s. - when the vector length is 16 bytes (VLEN=3D128) and there's no grouping o= f the vector registers (LMUL=3D1). The optimization consists of avoiding the overhead of probing the RAM of the host machine and doing a loop load/store on the input data grouped in chunks of as many bytes as possible (8,4,2,1 bytes). Co-authored-by: Helene CHELIN Co-authored-by: Paolo Savini Signed-off-by: Helene CHELIN Signed-off-by: Paolo Savini Reviewed-by: Daniel Henrique Barboza --- target/riscv/vector_helper.c | 47 ++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 4479726acf..75c24653f0 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -635,6 +635,53 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVStat= e *env, uint32_t desc, =20 VSTART_CHECK_EARLY_EXIT(env); =20 +#if defined(CONFIG_USER_ONLY) && !HOST_BIG_ENDIAN + /* For data sizes <=3D 64 bits and for LMUL=3D1 with VLEN=3D128 bits w= e get a + * better performance by doing a simple simulation of the load/store + * without the overhead of prodding the host RAM */ + if ((nf =3D=3D 1) && ((evl << log2_esz) <=3D 8 || + ((vext_lmul(desc) =3D=3D 0) && (simd_maxsz(desc) =3D=3D 16)))) { + + uint32_t evl_b =3D evl << log2_esz; + + for (uint32_t j =3D env->vstart; j < evl_b;) { + addr =3D base + j; + if ((evl_b - j) >=3D 8) { + if (is_load) + lde_d_tlb(env, adjust_addr(env, addr), j, vd, ra); + else + ste_d_tlb(env, adjust_addr(env, addr), j, vd, ra); + j +=3D 8; + } + else if ((evl_b - j) >=3D 4) { + if (is_load) + lde_w_tlb(env, adjust_addr(env, addr), j, vd, ra); + else + ste_w_tlb(env, adjust_addr(env, addr), j, vd, ra); + j +=3D 4; + } + else if ((evl_b - j) >=3D 2) { + if (is_load) + lde_h_tlb(env, adjust_addr(env, addr), j, vd, ra); + else + ste_h_tlb(env, adjust_addr(env, addr), j, vd, ra); + j +=3D 2; + } + else { + if (is_load) + lde_b_tlb(env, adjust_addr(env, addr), j, vd, ra); + else + ste_b_tlb(env, adjust_addr(env, addr), j, vd, ra); + j +=3D 1; + } + } + + env->vstart =3D 0; + vext_set_tail_elems_1s(evl, vd, desc, nf, esz, max_elems); + return; + } +#endif + vext_cont_ldst_elements(&info, base, env->vreg, env->vstart, evl, desc, log2_esz, false); /* Probe the page(s). Exit with exception for any invalid page. */ --=20 2.34.1