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a="31334458" X-IronPort-AV: E=Sophos;i="6.12,144,1728975600"; d="scan'208";a="31334458" X-CSE-ConnectionGUID: rMVQtBFrTzevEFxoqi3S7g== X-CSE-MsgGUID: ahhb2B9tQOeJYvUzClH3CQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,144,1728975600"; d="scan'208";a="87608322" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, peterx@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PATCH v5 10/20] intel_iommu: Flush stage-1 cache in iotlb invalidation Date: Mon, 11 Nov 2024 16:34:47 +0800 Message-Id: <20241111083457.2090664-11-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241111083457.2090664-1-zhenzhong.duan@intel.com> References: <20241111083457.2090664-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.14; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -44 X-Spam_score: -4.5 X-Spam_bar: ---- X-Spam_report: (-4.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.118, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1731314542784116600 According to spec, Page-Selective-within-Domain Invalidation (11b): 1. IOTLB entries caching second-stage mappings (PGTT=3D010b) or pass-through (PGTT=3D100b) mappings associated with the specified domain-id and the input-address range are invalidated. 2. IOTLB entries caching first-stage (PGTT=3D001b) or nested (PGTT=3D011b) mapping associated with specified domain-id are invalidated. So per spec definition the Page-Selective-within-Domain Invalidation needs to flush first stage and nested cached IOTLB enties as well. We don't support nested yet and pass-through mapping is never cached, so what in iotlb cache are only first-stage and second-stage mappings. Add a tag pgtt in VTDIOTLBEntry to mark PGTT type of the mapping and invalidate entries based on PGTT type. Signed-off-by: Zhenzhong Duan Reviewed-by: Cl=C3=A9ment Mathieu--Drif Acked-by: Jason Wang Reviewed-by: Yi Liu --- include/hw/i386/intel_iommu.h | 1 + hw/i386/intel_iommu.c | 27 +++++++++++++++++++++------ 2 files changed, 22 insertions(+), 6 deletions(-) diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 100b1d7673..13e8680b87 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -155,6 +155,7 @@ struct VTDIOTLBEntry { uint64_t pte; uint64_t mask; uint8_t access_flags; + uint8_t pgtt; }; =20 /* VT-d Source-ID Qualifier types */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 5af61478ac..4b0fb1f83d 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -305,9 +305,21 @@ static gboolean vtd_hash_remove_by_page(gpointer key, = gpointer value, VTDIOTLBPageInvInfo *info =3D (VTDIOTLBPageInvInfo *)user_data; uint64_t gfn =3D (info->addr >> VTD_PAGE_SHIFT_4K) & info->mask; uint64_t gfn_tlb =3D (info->addr & entry->mask) >> VTD_PAGE_SHIFT_4K; - return (entry->domain_id =3D=3D info->domain_id) && - (((entry->gfn & info->mask) =3D=3D gfn) || - (entry->gfn =3D=3D gfn_tlb)); + + if (entry->domain_id !=3D info->domain_id) { + return false; + } + + /* + * According to spec, IOTLB entries caching first-stage (PGTT=3D001b) = or + * nested (PGTT=3D011b) mapping associated with specified domain-id are + * invalidated. Nested isn't supported yet, so only need to check 001b. + */ + if (entry->pgtt =3D=3D VTD_SM_PASID_ENTRY_FLT) { + return true; + } + + return (entry->gfn & info->mask) =3D=3D gfn || entry->gfn =3D=3D gfn_t= lb; } =20 /* Reset all the gen of VTDAddressSpace to zero and set the gen of @@ -382,7 +394,7 @@ out: static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t source_id, uint16_t domain_id, hwaddr addr, uint64_t pte, uint8_t access_flags, uint32_t level, - uint32_t pasid) + uint32_t pasid, uint8_t pgtt) { VTDIOTLBEntry *entry =3D g_malloc(sizeof(*entry)); struct vtd_iotlb_key *key =3D g_malloc(sizeof(*key)); @@ -400,6 +412,7 @@ static void vtd_update_iotlb(IntelIOMMUState *s, uint16= _t source_id, entry->access_flags =3D access_flags; entry->mask =3D vtd_pt_level_page_mask(level); entry->pasid =3D pasid; + entry->pgtt =3D pgtt; =20 key->gfn =3D gfn; key->sid =3D source_id; @@ -2062,7 +2075,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *v= td_as, PCIBus *bus, bool is_fpd_set =3D false; bool reads =3D true; bool writes =3D true; - uint8_t access_flags; + uint8_t access_flags, pgtt; bool rid2pasid =3D (pasid =3D=3D PCI_NO_PASID) && s->root_scalable; VTDIOTLBEntry *iotlb_entry; uint64_t xlat, size; @@ -2171,9 +2184,11 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *= vtd_as, PCIBus *bus, if (s->scalable_modern && s->root_scalable) { ret_fr =3D vtd_iova_to_flpte(s, &ce, addr, is_write, &pte, &level, &reads, &writes, s->aw_bits, pasid); + pgtt =3D VTD_SM_PASID_ENTRY_FLT; } else { ret_fr =3D vtd_iova_to_slpte(s, &ce, addr, is_write, &pte, &level, &reads, &writes, s->aw_bits, pasid); + pgtt =3D VTD_SM_PASID_ENTRY_SLT; } if (!ret_fr) { xlat =3D vtd_get_pte_addr(pte, s->aw_bits); @@ -2207,7 +2222,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *v= td_as, PCIBus *bus, page_mask =3D vtd_pt_level_page_mask(level); access_flags =3D IOMMU_ACCESS_FLAG(reads, writes); vtd_update_iotlb(s, source_id, vtd_get_domain_id(s, &ce, pasid), - addr, pte, access_flags, level, pasid); + addr, pte, access_flags, level, pasid, pgtt); out: vtd_iommu_unlock(s); entry->iova =3D addr & page_mask; --=20 2.34.1