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Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann Subject: [PATCH 1/2] hw/usb: Make PCI device more configurable Date: Sun, 10 Nov 2024 15:00:07 +1000 Message-ID: <20241110050009.389367-2-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241110050009.389367-1-npiggin@gmail.com> References: <20241110050009.389367-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=npiggin@gmail.com; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1731214871214116600 Content-Type: text/plain; charset="utf-8" To prepare to support another USB PCI Host Controller, make some PCI configuration dynamic. Signed-off-by: Nicholas Piggin --- hw/usb/hcd-xhci-pci.h | 9 ++++++ hw/usb/hcd-xhci-nec.c | 10 +++++++ hw/usb/hcd-xhci-pci.c | 69 ++++++++++++++++++++++++++++++++++++------- 3 files changed, 78 insertions(+), 10 deletions(-) diff --git a/hw/usb/hcd-xhci-pci.h b/hw/usb/hcd-xhci-pci.h index 08f70ce97c..213076aabf 100644 --- a/hw/usb/hcd-xhci-pci.h +++ b/hw/usb/hcd-xhci-pci.h @@ -40,6 +40,15 @@ typedef struct XHCIPciState { XHCIState xhci; OnOffAuto msi; OnOffAuto msix; + uint8_t cache_line_size; + uint8_t pm_cap_off; + uint8_t pcie_cap_off; + uint8_t msi_cap_off; + uint8_t msix_cap_off; + int msix_bar_nr; + uint64_t msix_bar_size; + uint32_t msix_table_off; + uint32_t msix_pba_off; } XHCIPciState; =20 #endif diff --git a/hw/usb/hcd-xhci-nec.c b/hw/usb/hcd-xhci-nec.c index 0c063b3697..e23b5ff084 100644 --- a/hw/usb/hcd-xhci-nec.c +++ b/hw/usb/hcd-xhci-nec.c @@ -54,6 +54,16 @@ static void nec_xhci_instance_init(Object *obj) pci->xhci.flags =3D nec->flags; pci->xhci.numintrs =3D nec->intrs; pci->xhci.numslots =3D nec->slots; + + pci->cache_line_size =3D 0x10; + pci->pm_cap_off =3D 0; + pci->pcie_cap_off =3D 0xa0; + pci->msi_cap_off =3D 0x70; + pci->msix_cap_off =3D 0x90; + pci->msix_bar_nr =3D 0; + pci->msix_bar_size =3D 0; + pci->msix_table_off =3D 0x3000; + pci->msix_pba_off =3D 0x3800; } =20 static void nec_xhci_class_init(ObjectClass *klass, void *data) diff --git a/hw/usb/hcd-xhci-pci.c b/hw/usb/hcd-xhci-pci.c index a039f5778a..948d75b737 100644 --- a/hw/usb/hcd-xhci-pci.c +++ b/hw/usb/hcd-xhci-pci.c @@ -32,8 +32,9 @@ #include "trace.h" #include "qapi/error.h" =20 -#define OFF_MSIX_TABLE 0x3000 -#define OFF_MSIX_PBA 0x3800 +#define MSIX_BAR_SIZE 0x800000 +#define OFF_MSIX_TABLE 0x0000 +#define OFF_MSIX_PBA 0x1000 =20 static void xhci_pci_intr_update(XHCIState *xhci, int n, bool enable) { @@ -104,6 +105,31 @@ static int xhci_pci_vmstate_post_load(void *opaque, in= t version_id) return 0; } =20 +static int xhci_pci_add_pm_capability(PCIDevice *pci_dev, uint8_t offset, + Error **errp) +{ + int err; + + err =3D pci_add_capability(pci_dev, PCI_CAP_ID_PM, offset, + PCI_PM_SIZEOF, errp); + if (err < 0) { + return err; + } + + pci_set_word(pci_dev->config + offset + PCI_PM_PMC, + PCI_PM_CAP_VER_1_2 | + PCI_PM_CAP_D1 | PCI_PM_CAP_D2 | + PCI_PM_CAP_PME_D0 | PCI_PM_CAP_PME_D1 | + PCI_PM_CAP_PME_D2 | PCI_PM_CAP_PME_D3hot); + pci_set_word(pci_dev->wmask + offset + PCI_PM_PMC, 0); + pci_set_word(pci_dev->config + offset + PCI_PM_CTRL, + PCI_PM_CTRL_NO_SOFT_RESET); + pci_set_word(pci_dev->wmask + offset + PCI_PM_CTRL, + PCI_PM_CTRL_STATE_MASK); + + return 0; +} + static void usb_xhci_pci_realize(struct PCIDevice *dev, Error **errp) { int ret; @@ -112,7 +138,7 @@ static void usb_xhci_pci_realize(struct PCIDevice *dev,= Error **errp) =20 dev->config[PCI_CLASS_PROG] =3D 0x30; /* xHCI */ dev->config[PCI_INTERRUPT_PIN] =3D 0x01; /* interrupt pin 1 */ - dev->config[PCI_CACHE_LINE_SIZE] =3D 0x10; + dev->config[PCI_CACHE_LINE_SIZE] =3D s->cache_line_size; dev->config[0x60] =3D 0x30; /* release number */ =20 object_property_set_link(OBJECT(&s->xhci), "host", OBJECT(s), NULL); @@ -125,8 +151,16 @@ static void usb_xhci_pci_realize(struct PCIDevice *dev= , Error **errp) s->xhci.nec_quirks =3D true; } =20 + if (s->pm_cap_off) { + if (xhci_pci_add_pm_capability(dev, s->pm_cap_off, &err)) { + error_propagate(errp, err); + return; + } + } + if (s->msi !=3D ON_OFF_AUTO_OFF) { - ret =3D msi_init(dev, 0x70, s->xhci.numintrs, true, false, &err); + ret =3D msi_init(dev, s->msi_cap_off, s->xhci.numintrs, + true, false, &err); /* * Any error other than -ENOTSUP(board's MSI support is broken) * is a programming error @@ -143,22 +177,37 @@ static void usb_xhci_pci_realize(struct PCIDevice *de= v, Error **errp) /* With msi=3Dauto, we fall back to MSI off silently */ error_free(err); } + pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, &s->xhci.mem); =20 if (pci_bus_is_express(pci_get_bus(dev))) { - ret =3D pcie_endpoint_cap_init(dev, 0xa0); + ret =3D pcie_endpoint_cap_init(dev, s->pcie_cap_off); assert(ret > 0); } =20 if (s->msix !=3D ON_OFF_AUTO_OFF) { - /* TODO check for errors, and should fail when msix=3Don */ - msix_init(dev, s->xhci.numintrs, - &s->xhci.mem, 0, OFF_MSIX_TABLE, - &s->xhci.mem, 0, OFF_MSIX_PBA, - 0x90, NULL); + MemoryRegion *msix_bar =3D &s->xhci.mem; + if (s->msix_bar_nr !=3D 0) { + memory_region_init(&dev->msix_exclusive_bar, OBJECT(dev), + "xhci-msix", s->msix_bar_size); + msix_bar =3D &dev->msix_exclusive_bar; + } + + ret =3D msix_init(dev, s->xhci.numintrs, + msix_bar, s->msix_bar_nr, s->msix_table_off, + msix_bar, s->msix_bar_nr, s->msix_pba_off, + s->msix_cap_off, errp); + if (ret) { + return; + } + + pci_register_bar(dev, s->msix_bar_nr, + PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_TYPE_64, + msix_bar); } s->xhci.as =3D pci_get_address_space(dev); } --=20 2.45.2 From nobody Sat Nov 23 19:54:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1731214870; cv=none; d=zohomail.com; s=zohoarc; b=X1zbb4GToFOBEiY5cv/6LByyoDKAeDccRd8oHwyY4X/d9mNd4aFx+Ln4dltMNAgMDGG9A82WpyKr8z+7l0aVcz6I4nIeEtXxFsQmvoZYHogWraDIWfAkoj0KlZzbmmK0bZaSfeOtuzUvaT7Rwp9eRB8Us90pkzccahwujvB57mw= ARC-Message-Signature: i=1; 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Tsirkin" , Marcel Apfelbaum , Gerd Hoffmann Subject: [PATCH 2/2] hw/usb: Add TI TUSB73X0 XHCI controller model Date: Sun, 10 Nov 2024 15:00:08 +1000 Message-ID: <20241110050009.389367-3-npiggin@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20241110050009.389367-1-npiggin@gmail.com> References: <20241110050009.389367-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=npiggin@gmail.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1731214871377116600 Content-Type: text/plain; charset="utf-8" This controller is accepted by IBM Power firmware when the subsystem IDs are set to Power servers. Firmware is picky about device support so the NEC driver does not work. The TI HW has some interesting differences from NEC, notably a separate BAR for MSIX, and PM capabilities. The spec is freely available without sign-up. Signed-off-by: Nicholas Piggin --- include/hw/pci/pci_ids.h | 1 + include/hw/usb/xhci.h | 1 + hw/usb/hcd-xhci-ti.c | 94 ++++++++++++++++++++++++++++++++++++++++ hw/usb/Kconfig | 5 +++ hw/usb/meson.build | 1 + 5 files changed, 102 insertions(+) create mode 100644 hw/usb/hcd-xhci-ti.c diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h index f1a53fea8d..fdb692db51 100644 --- a/include/hw/pci/pci_ids.h +++ b/include/hw/pci/pci_ids.h @@ -182,6 +182,7 @@ #define PCI_VENDOR_ID_HP 0x103c =20 #define PCI_VENDOR_ID_TI 0x104c +#define PCI_DEVICE_ID_TI_TUSB73X0 0x8241 =20 #define PCI_VENDOR_ID_MOTOROLA 0x1057 #define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002 diff --git a/include/hw/usb/xhci.h b/include/hw/usb/xhci.h index 5c90e1373e..203ec1fca3 100644 --- a/include/hw/usb/xhci.h +++ b/include/hw/usb/xhci.h @@ -3,6 +3,7 @@ =20 #define TYPE_XHCI "base-xhci" #define TYPE_NEC_XHCI "nec-usb-xhci" +#define TYPE_TI_XHCI "ti-usb-xhci" #define TYPE_QEMU_XHCI "qemu-xhci" #define TYPE_XHCI_SYSBUS "sysbus-xhci" =20 diff --git a/hw/usb/hcd-xhci-ti.c b/hw/usb/hcd-xhci-ti.c new file mode 100644 index 0000000000..a3f7ef8ba2 --- /dev/null +++ b/hw/usb/hcd-xhci-ti.c @@ -0,0 +1,94 @@ +/* + * USB xHCI controller emulation + * Datasheet https://www.ti.com/product/TUSB7340 + * + * Copyright (c) 2011 Securiforest + * Date: 2011-05-11 ; Author: Hector Martin + * Based on usb-xhci-nec.c, emulates TI TUSB73X0 + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "hw/usb.h" +#include "qemu/module.h" +#include "hw/pci/pci.h" +#include "hw/qdev-properties.h" + +#include "hcd-xhci-pci.h" + +OBJECT_DECLARE_SIMPLE_TYPE(XHCITiState, TI_XHCI) + +struct XHCITiState { + /*< private >*/ + XHCIPciState parent_obj; + /*< public >*/ + uint32_t flags; + uint32_t intrs; + uint32_t slots; +}; + +static Property ti_xhci_properties[] =3D { + DEFINE_PROP_ON_OFF_AUTO("msi", XHCIPciState, msi, ON_OFF_AUTO_AUTO), + DEFINE_PROP_ON_OFF_AUTO("msix", XHCIPciState, msix, ON_OFF_AUTO_AUTO), + DEFINE_PROP_UINT32("intrs", XHCITiState, intrs, 8), + DEFINE_PROP_UINT32("slots", XHCITiState, slots, XHCI_MAXSLOTS), + DEFINE_PROP_END_OF_LIST(), +}; + +static void ti_xhci_instance_init(Object *obj) +{ + XHCIPciState *pci =3D XHCI_PCI(obj); + XHCITiState *ti =3D TI_XHCI(obj); + + pci->xhci.flags =3D ti->flags; + pci->xhci.numintrs =3D ti->intrs; + pci->xhci.numslots =3D ti->slots; + + pci->cache_line_size =3D 0x0; + pci->pm_cap_off =3D 0x40; + pci->pcie_cap_off =3D 0x70; + pci->msi_cap_off =3D 0x48; + pci->msix_cap_off =3D 0xc0; + pci->msix_bar_nr =3D 0x2; + pci->msix_bar_size =3D 0x800000; + pci->msix_table_off =3D 0x0; + pci->msix_pba_off =3D 0x1000; +} + +static void ti_xhci_class_init(ObjectClass *klass, void *data) +{ + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + + device_class_set_props(dc, ti_xhci_properties); + k->vendor_id =3D PCI_VENDOR_ID_TI; + k->device_id =3D PCI_DEVICE_ID_TI_TUSB73X0; + k->revision =3D 0x02; +} + +static const TypeInfo ti_xhci_info =3D { + .name =3D TYPE_TI_XHCI, + .parent =3D TYPE_XHCI_PCI, + .instance_size =3D sizeof(XHCITiState), + .instance_init =3D ti_xhci_instance_init, + .class_init =3D ti_xhci_class_init, +}; + +static void ti_xhci_register_types(void) +{ + type_register_static(&ti_xhci_info); +} + +type_init(ti_xhci_register_types) diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig index 5fbecd2f43..8e5c4747af 100644 --- a/hw/usb/Kconfig +++ b/hw/usb/Kconfig @@ -49,6 +49,11 @@ config USB_XHCI_NEC default y if PCI_DEVICES select USB_XHCI_PCI =20 +config USB_XHCI_TI + bool + default y if PCI_DEVICES + select USB_XHCI_PCI + config USB_XHCI_SYSBUS bool select USB_XHCI diff --git a/hw/usb/meson.build b/hw/usb/meson.build index 1b4d1507e4..b874a93f16 100644 --- a/hw/usb/meson.build +++ b/hw/usb/meson.build @@ -23,6 +23,7 @@ system_ss.add(when: 'CONFIG_USB_XHCI', if_true: files('hc= d-xhci.c')) system_ss.add(when: 'CONFIG_USB_XHCI_PCI', if_true: files('hcd-xhci-pci.c'= )) system_ss.add(when: 'CONFIG_USB_XHCI_SYSBUS', if_true: files('hcd-xhci-sys= bus.c')) system_ss.add(when: 'CONFIG_USB_XHCI_NEC', if_true: files('hcd-xhci-nec.c'= )) +system_ss.add(when: 'CONFIG_USB_XHCI_TI', if_true: files('hcd-xhci-ti.c')) system_ss.add(when: 'CONFIG_USB_DWC2', if_true: files('hcd-dwc2.c')) system_ss.add(when: 'CONFIG_USB_DWC3', if_true: files('hcd-dwc3.c')) =20 --=20 2.45.2