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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1149; envelope-from=3LmIuZwYKCusebdhRUTbbTYR.PbZdRZh-QRiRYabaTah.beT@flex--roqueh.bounces.google.com; helo=mail-yw1-x1149.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1731093131531116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The following tests focus on making sure the counter is not running out of reset and the proper use of INTEN as the counter enable. As described in: https://developer.arm.com/documentation/ddi0479/d/apb-components/apb-watchd= og/programmers-model The new tests have to target an MPS2 machine because the original machine used by the test (stellaris) has a variation of the cmsdk_apb_watchdog that locks INTEN when it is programmed to 1. The stellaris machine also does not reproduce the problem of the counter running out of cold reset due to the way the clocks are initialized. Signed-off-by: Roque Arcudia Hernandez Reviewed-by: Stephen Longfield --- tests/qtest/cmsdk-apb-watchdog-test.c | 214 ++++++++++++++++++++++++++ 1 file changed, 214 insertions(+) diff --git a/tests/qtest/cmsdk-apb-watchdog-test.c b/tests/qtest/cmsdk-apb-= watchdog-test.c index fe535a553c..3777b7bd59 100644 --- a/tests/qtest/cmsdk-apb-watchdog-test.c +++ b/tests/qtest/cmsdk-apb-watchdog-test.c @@ -68,6 +68,15 @@ static const CMSDKAPBWatchdogTestArgs machine_info[] =3D= { }, }; =20 +static void system_reset(QTestState *qtest) +{ + QDict *resp; + + resp =3D qtest_qmp(qtest, "{'execute': 'system_reset'}"); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); +} + static void test_watchdog(const void *ptr) { const CMSDKAPBWatchdogTestArgs *args =3D ptr; @@ -159,6 +168,199 @@ static void test_clock_change(const void *ptr) qtest_end(); } =20 +/* Tests the counter is not running after reset. */ +static void test_watchdog_reset(const void *ptr) +{ + const CMSDKAPBWatchdogTestArgs *args =3D ptr; + hwaddr wdog_base =3D args->wdog_base; + int64_t tick =3D args->tick; + g_autofree gchar *cmdline =3D g_strdup_printf("-machine %s", args->mac= hine); + qtest_start(cmdline); + g_assert_cmpuint(readl(wdog_base + WDOGRIS), =3D=3D, 0); + + g_assert_cmphex(readl(wdog_base + WDOGLOAD), =3D=3D, WDOGLOAD_DEFAULT); + g_assert_cmphex(readl(wdog_base + WDOGVALUE), =3D=3D, WDOGVALUE_DEFAUL= T); + + g_assert_cmphex(readl(wdog_base + WDOGCONTROL), =3D=3D, 0); + + /* + * The counter should not be running if WDOGCONTROL.INTEN has not been= set, + * as it is the case after a cold reset. + */ + clock_step(15 * tick + 1); + g_assert_cmphex(readl(wdog_base + WDOGLOAD), =3D=3D, WDOGLOAD_DEFAULT); + g_assert_cmphex(readl(wdog_base + WDOGVALUE), =3D=3D, WDOGVALUE_DEFAUL= T); + + /* Let the counter run before reset */ + writel(wdog_base + WDOGLOAD, 3000); + writel(wdog_base + WDOGCONTROL, 1); + + /* Verify it is running */ + clock_step(1000 * tick + 1); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 3000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 2000); + + system_reset(global_qtest); + + /* Check defaults after reset */ + g_assert_cmphex(readl(wdog_base + WDOGLOAD), =3D=3D, WDOGLOAD_DEFAULT); + g_assert_cmphex(readl(wdog_base + WDOGVALUE), =3D=3D, WDOGVALUE_DEFAUL= T); + + /* The counter should not be running after reset. */ + clock_step(1000 * tick + 1); + g_assert_cmphex(readl(wdog_base + WDOGLOAD), =3D=3D, WDOGLOAD_DEFAULT); + g_assert_cmphex(readl(wdog_base + WDOGVALUE), =3D=3D, WDOGVALUE_DEFAUL= T); + + qtest_end(); +} + +/* + * Tests inten works as the counter enable based on this description: + * + * Enable the interrupt event, WDOGINT. Set HIGH to enable the counter and= the + * interrupt, or LOW to disable the counter and interrupt. Reloads the cou= nter + * from the value in WDOGLOAD when the interrupt is enabled, after previou= sly + * being disabled. + */ +static void test_watchdog_inten(const void *ptr) +{ + const CMSDKAPBWatchdogTestArgs *args =3D ptr; + hwaddr wdog_base =3D args->wdog_base; + int64_t tick =3D args->tick; + g_autofree gchar *cmdline =3D g_strdup_printf("-machine %s", args->mac= hine); + qtest_start(cmdline); + g_assert_cmpuint(readl(wdog_base + WDOGRIS), =3D=3D, 0); + + g_assert_cmphex(readl(wdog_base + WDOGLOAD), =3D=3D, WDOGLOAD_DEFAULT); + g_assert_cmphex(readl(wdog_base + WDOGVALUE), =3D=3D, WDOGVALUE_DEFAUL= T); + + /* + * When WDOGLOAD is written to, the count is immediately restarted fro= m the + * new value. + * + * Note: the counter should not be running as long as WDOGCONTROL.INTE= N is + * not set + */ + writel(wdog_base + WDOGLOAD, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 4000); + clock_step(500 * tick + 1); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 4000); + + /* Set HIGH WDOGCONTROL.INTEN to enable the counter and the interrupt = */ + writel(wdog_base + WDOGCONTROL, 1); + clock_step(500 * tick + 1); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 3500); + + /* or LOW to disable the counter and interrupt. */ + writel(wdog_base + WDOGCONTROL, 0); + clock_step(100 * tick); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 3500); + + /* + * Reloads the counter from the value in WDOGLOAD when the interrupt is + * enabled, after previously being disabled. + */ + writel(wdog_base + WDOGCONTROL, 1); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 4000); + + /* Test counter is still on */ + clock_step(50 * tick + 1); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 3950); + + /* + * When WDOGLOAD is written to, the count is immediately restarted fro= m the + * new value. + * + * Note: the counter should be running since WDOGCONTROL.INTEN is set + */ + writel(wdog_base + WDOGLOAD, 5000); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 5000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 5000); + clock_step(4999 * tick + 1); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 5000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 1); + g_assert_cmpuint(readl(wdog_base + WDOGRIS), =3D=3D, 0); + + /* Finally disable and check the conditions don't change */ + writel(wdog_base + WDOGCONTROL, 0); + clock_step(10 * tick); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 5000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 1); + g_assert_cmpuint(readl(wdog_base + WDOGRIS), =3D=3D, 0); + + qtest_end(); +} + +/* + * Tests the following custom behavior: + * + * The Luminary version of this device ignores writes to this register aft= er the + * guest has enabled interrupts (so they can only be disabled again via re= set). + */ +static void test_watchdog_inten_luminary(const void *ptr) +{ + const CMSDKAPBWatchdogTestArgs *args =3D ptr; + hwaddr wdog_base =3D args->wdog_base; + int64_t tick =3D args->tick; + g_autofree gchar *cmdline =3D g_strdup_printf("-machine %s", args->mac= hine); + qtest_start(cmdline); + g_assert_cmpuint(readl(wdog_base + WDOGRIS), =3D=3D, 0); + + g_assert_cmphex(readl(wdog_base + WDOGLOAD), =3D=3D, WDOGLOAD_DEFAULT); + g_assert_cmphex(readl(wdog_base + WDOGVALUE), =3D=3D, WDOGVALUE_DEFAUL= T); + + /* + * When WDOGLOAD is written to, the count is immediately restarted fro= m the + * new value. + * + * Note: the counter should not be running as long as WDOGCONTROL.INTE= N is + * not set + */ + writel(wdog_base + WDOGLOAD, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 4000); + clock_step(500 * tick + 1); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 4000); + + /* Set HIGH WDOGCONTROL.INTEN to enable the counter and the interrupt = */ + writel(wdog_base + WDOGCONTROL, 1); + clock_step(500 * tick + 1); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 3500); + + /* + * The Luminary version of this device ignores writes to this register= after + * the guest has enabled interrupts + */ + writel(wdog_base + WDOGCONTROL, 0); + clock_step(100 * tick); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 3400); + g_assert_cmphex(readl(wdog_base + WDOGCONTROL), =3D=3D, 0x1); + + /* They can only be disabled again via reset */ + system_reset(global_qtest); + + /* Check defaults after reset */ + g_assert_cmphex(readl(wdog_base + WDOGLOAD), =3D=3D, WDOGLOAD_DEFAULT); + g_assert_cmphex(readl(wdog_base + WDOGVALUE), =3D=3D, WDOGVALUE_DEFAUL= T); + g_assert_cmphex(readl(wdog_base + WDOGCONTROL), =3D=3D, 0); + + /* The counter should not be running after reset. */ + clock_step(1000 * tick + 1); + g_assert_cmphex(readl(wdog_base + WDOGLOAD), =3D=3D, WDOGLOAD_DEFAULT); + g_assert_cmphex(readl(wdog_base + WDOGVALUE), =3D=3D, WDOGVALUE_DEFAUL= T); + + qtest_end(); +} + int main(int argc, char **argv) { int r; @@ -172,10 +374,22 @@ int main(int argc, char **argv) qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_clock_change", &machine_info[MACHINE_LM3S811EVB], test_clock_change); + qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_reset", + &machine_info[MACHINE_LM3S811EVB], + test_watchdog_reset); + qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_inten_luminary", + &machine_info[MACHINE_LM3S811EVB], + test_watchdog_inten_luminary); } if (qtest_has_machine(machine_info[MACHINE_MPS2_AN385].machine)) { qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_mps2", &machine_info[MACHINE_MPS2_AN385], test_watchd= og); + qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_reset_mps2", + &machine_info[MACHINE_MPS2_AN385], + test_watchdog_reset); + qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_inten", + &machine_info[MACHINE_MPS2_AN385], + test_watchdog_inten); } =20 r =3D g_test_run(); --=20 2.47.0.277.g8800431eea-goog