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charset="utf-8" Current watchdog is free running out of reset, this combined with the fact that current implementation also ensures the counter is running when programing WDOGLOAD creates issues when the firmware defer the programing of WDOGCONTROL.INTEN much later after WDOGLOAD. Arm Programmer's Model documentation states that INTEN is also the counter enable: > INTEN > > Enable the interrupt event, WDOGINT. Set HIGH to enable the counter > and the interrupt, or LOW to disable the counter and interrupt. > Reloads the counter from the value in WDOGLOAD when the interrupt > is enabled, after previously being disabled. Source of the time of writing: https://developer.arm.com/documentation/ddi0479/d/apb-components/apb-watchd= og/programmers-model Signed-off-by: Roque Arcudia Hernandez Reviewed-by: Stephen Longfield Reviewed-by: Joe Komlodi --- hw/watchdog/cmsdk-apb-watchdog.c | 29 ++++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watch= dog.c index 7ad46f9410..e6ddc0a53b 100644 --- a/hw/watchdog/cmsdk-apb-watchdog.c +++ b/hw/watchdog/cmsdk-apb-watchdog.c @@ -202,10 +202,10 @@ static void cmsdk_apb_watchdog_write(void *opaque, hw= addr offset, */ ptimer_transaction_begin(s->timer); ptimer_set_limit(s->timer, value, 1); - ptimer_run(s->timer, 0); ptimer_transaction_commit(s->timer); break; - case A_WDOGCONTROL: + case A_WDOGCONTROL: { + uint32_t prev_control =3D s->control; if (s->is_luminary && 0 !=3D (R_WDOGCONTROL_INTEN_MASK & s->contro= l)) { /* * The Luminary version of this device ignores writes to @@ -215,8 +215,25 @@ static void cmsdk_apb_watchdog_write(void *opaque, hwa= ddr offset, break; } s->control =3D value & R_WDOGCONTROL_VALID_MASK; + if (R_WDOGCONTROL_INTEN_MASK & (s->control ^ prev_control)) { + ptimer_transaction_begin(s->timer); + if (R_WDOGCONTROL_INTEN_MASK & s->control) { + /* + * Set HIGH to enable the counter and the interrupt. Reloa= ds + * the counter from the value in WDOGLOAD when the interru= pt + * is enabled, after previously being disabled. + */ + ptimer_set_count(s->timer, ptimer_get_limit(s->timer)); + ptimer_run(s->timer, 0); + } else { + /* Or LOW to disable the counter and interrupt. */ + ptimer_stop(s->timer); + } + ptimer_transaction_commit(s->timer); + } cmsdk_apb_watchdog_update(s); break; + } case A_WDOGINTCLR: s->intstatus =3D 0; ptimer_transaction_begin(s->timer); @@ -305,8 +322,14 @@ static void cmsdk_apb_watchdog_reset(DeviceState *dev) s->resetstatus =3D 0; /* Set the limit and the count */ ptimer_transaction_begin(s->timer); + /* + * We need to stop the ptimer before setting its limit reset value. If= the + * order is the opposite when the code executes the stop after setting= a new + * limit it may want to recalculate the count based on the current tim= e (if + * the timer was currently running) and it won't get the proper reset = value. + */ + ptimer_stop(s->timer); ptimer_set_limit(s->timer, 0xffffffff, 1); - ptimer_run(s->timer, 0); ptimer_transaction_commit(s->timer); } =20 --=20 2.47.0.277.g8800431eea-goog From nobody Sat Nov 23 20:05:32 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1731093109; cv=none; d=zohomail.com; s=zohoarc; b=AkZD843tHG5odFkjXau8svfHoAPH5YjurJuzsXswjRPkxPtr1a+wqQhLHdUTJOAfQQ7exmr1wprUlmb6NQv8LCTA/UpBVLdQwh/FILOhni7MNVepN11DxpeiKDGGAsoU4OhOpyBcsKsR3uU2gkxdLnBABg3LSZdAblClEbRwv9Q= ARC-Message-Signature: i=1; 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Fri, 08 Nov 2024 11:10:34 -0800 (PST) Date: Fri, 8 Nov 2024 19:10:23 +0000 In-Reply-To: <20241108191024.2931097-1-roqueh@google.com> Mime-Version: 1.0 References: <20241108191024.2931097-1-roqueh@google.com> X-Mailer: git-send-email 2.47.0.277.g8800431eea-goog Message-ID: <20241108191024.2931097-3-roqueh@google.com> Subject: [PATCH 2/3] tests/qtest/cmsdk-apb-watchdog-test: Parameterize tests From: Roque Arcudia Hernandez To: peter.maydell@linaro.org, farosas@suse.de, lvivier@redhat.com, slongfield@google.com, komlodi@google.com, pbonzini@redhat.com, venture@google.com Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Roque Arcudia Hernandez Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::114a; envelope-from=3KmIuZwYKCucaXZdNQPXXPUN.LXVZNVd-MNeNUWXWPWd.XaP@flex--roqueh.bounces.google.com; helo=mail-yw1-x114a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1731093111488116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently the CMSDK APB watchdog tests target an specialized version of the device (luminaris using the lm3s811evb machine) that prevents the development of tests for the more generic device documented in: https://developer.arm.com/documentation/ddi0479/d/apb-components/apb-watchd= og/programmers-model This patch allows the execution of the watchdog tests in an MPS2 machine (when applicable) which uses the generic version of the CMSDK APB watchdog. Finally the rules for compiling the test have to change because it is possible not to have CONFIG_STELLARIS (required for the lm3s811evb machine) while still having CONFIG_CMSDK_APB_WATCHDOG and the test will fail. Due to the addition of the MPS2 machine CONFIG_MPS2 becomes also a dependency for the test compilation. Signed-off-by: Roque Arcudia Hernandez Reviewed-by: Stephen Longfield --- tests/qtest/cmsdk-apb-watchdog-test.c | 115 +++++++++++++++++++------- tests/qtest/meson.build | 3 +- 2 files changed, 86 insertions(+), 32 deletions(-) diff --git a/tests/qtest/cmsdk-apb-watchdog-test.c b/tests/qtest/cmsdk-apb-= watchdog-test.c index 00b5dbbc81..fe535a553c 100644 --- a/tests/qtest/cmsdk-apb-watchdog-test.c +++ b/tests/qtest/cmsdk-apb-watchdog-test.c @@ -15,14 +15,12 @@ */ =20 #include "qemu/osdep.h" +#include "exec/hwaddr.h" #include "qemu/bitops.h" #include "libqtest-single.h" =20 -/* - * lm3s811evb watchdog; at board startup this runs at 200MHz / 16 =3D=3D 1= 2.5MHz, - * which is 80ns per tick. - */ #define WDOG_BASE 0x40000000 +#define WDOG_BASE_MPS2 0x40008000 =20 #define WDOGLOAD 0 #define WDOGVALUE 4 @@ -37,39 +35,87 @@ #define SYSDIV_SHIFT 23 #define SYSDIV_LENGTH 4 =20 -static void test_watchdog(void) +#define WDOGLOAD_DEFAULT 0xFFFFFFFF +#define WDOGVALUE_DEFAULT 0xFFFFFFFF + +typedef struct CMSDKAPBWatchdogTestArgs { + int64_t tick; + hwaddr wdog_base; + const char *machine; +} CMSDKAPBWatchdogTestArgs; + +enum { + MACHINE_LM3S811EVB, + MACHINE_MPS2_AN385, +}; + +/* + * lm3s811evb watchdog; at board startup this runs at 200MHz / 16 =3D=3D 1= 2.5MHz, + * which is 80ns per tick. + * + * IoTKit/ARMSSE dualtimer; driven at 25MHz in mps2-an385, so 40ns per tick + */ +static const CMSDKAPBWatchdogTestArgs machine_info[] =3D { + [MACHINE_LM3S811EVB] =3D { + .tick =3D 80, + .wdog_base =3D WDOG_BASE, + .machine =3D "lm3s811evb", + }, + [MACHINE_MPS2_AN385] =3D { + .tick =3D 40, + .wdog_base =3D WDOG_BASE_MPS2, + .machine =3D "mps2-an385", + }, +}; + +static void test_watchdog(const void *ptr) { - g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), =3D=3D, 0); + const CMSDKAPBWatchdogTestArgs *args =3D ptr; + hwaddr wdog_base =3D args->wdog_base; + int64_t tick =3D args->tick; + g_autofree gchar *cmdline =3D g_strdup_printf("-machine %s", args->mac= hine); + qtest_start(cmdline); =20 - writel(WDOG_BASE + WDOGCONTROL, 1); - writel(WDOG_BASE + WDOGLOAD, 1000); + g_assert_cmpuint(readl(wdog_base + WDOGRIS), =3D=3D, 0); + + writel(wdog_base + WDOGCONTROL, 1); + writel(wdog_base + WDOGLOAD, 1000); =20 /* Step to just past the 500th tick */ - clock_step(500 * 80 + 1); - g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), =3D=3D, 0); - g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), =3D=3D, 500); + clock_step(500 * tick + 1); + g_assert_cmpuint(readl(wdog_base + WDOGRIS), =3D=3D, 0); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 500); =20 /* Just past the 1000th tick: timer should have fired */ - clock_step(500 * 80); - g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), =3D=3D, 1); - g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), =3D=3D, 0); + clock_step(500 * tick); + g_assert_cmpuint(readl(wdog_base + WDOGRIS), =3D=3D, 1); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 0); =20 /* VALUE reloads at following tick */ - clock_step(80); - g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), =3D=3D, 1000); + clock_step(tick); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 1000); =20 /* Writing any value to WDOGINTCLR clears the interrupt and reloads */ - clock_step(500 * 80); - g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), =3D=3D, 500); - g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), =3D=3D, 1); - writel(WDOG_BASE + WDOGINTCLR, 0); - g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), =3D=3D, 1000); - g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), =3D=3D, 0); + clock_step(500 * tick); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 500); + g_assert_cmpuint(readl(wdog_base + WDOGRIS), =3D=3D, 1); + writel(wdog_base + WDOGINTCLR, 0); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 1000); + g_assert_cmpuint(readl(wdog_base + WDOGRIS), =3D=3D, 0); + + qtest_end(); } =20 -static void test_clock_change(void) +/* + * This test can only be executed in the stellaris board since it relies o= n a + * component of the board to change the clocking parameters of the watchdo= g. + */ +static void test_clock_change(const void *ptr) { uint32_t rcc; + const CMSDKAPBWatchdogTestArgs *args =3D ptr; + g_autofree gchar *cmdline =3D g_strdup_printf("-machine %s", args->mac= hine); + qtest_start(cmdline); =20 /* * Test that writing to the stellaris board's RCC register to @@ -109,6 +155,8 @@ static void test_clock_change(void) writel(WDOG_BASE + WDOGINTCLR, 0); g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), =3D=3D, 1000); g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), =3D=3D, 0); + + qtest_end(); } =20 int main(int argc, char **argv) @@ -116,16 +164,21 @@ int main(int argc, char **argv) int r; =20 g_test_init(&argc, &argv, NULL); - - qtest_start("-machine lm3s811evb"); - - qtest_add_func("/cmsdk-apb-watchdog/watchdog", test_watchdog); - qtest_add_func("/cmsdk-apb-watchdog/watchdog_clock_change", - test_clock_change); + g_test_set_nonfatal_assertions(); + + if (qtest_has_machine(machine_info[MACHINE_LM3S811EVB].machine)) { + qtest_add_data_func("/cmsdk-apb-watchdog/watchdog", + &machine_info[MACHINE_LM3S811EVB], test_watchd= og); + qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_clock_change", + &machine_info[MACHINE_LM3S811EVB], + test_clock_change); + } + if (qtest_has_machine(machine_info[MACHINE_MPS2_AN385].machine)) { + qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_mps2", + &machine_info[MACHINE_MPS2_AN385], test_watchd= og); + } =20 r =3D g_test_run(); =20 - qtest_end(); - return r; } diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index aa93e98418..f2f35367ae 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -227,7 +227,8 @@ qtests_arm =3D \ (config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \ (config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-= dualtimer-test'] : []) + \ (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-time= r-test'] : []) + \ - (config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-w= atchdog-test'] : []) + \ + (config_all_devices.has_key('CONFIG_STELLARIS') or + config_all_devices.has_key('CONFIG_MPS2') ? ['cmsdk-apb-watchdog-test']= : []) + \ (config_all_devices.has_key('CONFIG_PFLASH_CFI02') and config_all_devices.has_key('CONFIG_MUSICPAL') ? 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Fri, 08 Nov 2024 11:10:38 -0800 (PST) Date: Fri, 8 Nov 2024 19:10:24 +0000 In-Reply-To: <20241108191024.2931097-1-roqueh@google.com> Mime-Version: 1.0 References: <20241108191024.2931097-1-roqueh@google.com> X-Mailer: git-send-email 2.47.0.277.g8800431eea-goog Message-ID: <20241108191024.2931097-4-roqueh@google.com> Subject: [PATCH 3/3] tests/qtest/cmsdk-apb-watchdog-test: Test INTEN as counter enable From: Roque Arcudia Hernandez To: peter.maydell@linaro.org, farosas@suse.de, lvivier@redhat.com, slongfield@google.com, komlodi@google.com, pbonzini@redhat.com, venture@google.com Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Roque Arcudia Hernandez Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1149; envelope-from=3LmIuZwYKCusebdhRUTbbTYR.PbZdRZh-QRiRYabaTah.beT@flex--roqueh.bounces.google.com; helo=mail-yw1-x1149.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1731093131531116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The following tests focus on making sure the counter is not running out of reset and the proper use of INTEN as the counter enable. As described in: https://developer.arm.com/documentation/ddi0479/d/apb-components/apb-watchd= og/programmers-model The new tests have to target an MPS2 machine because the original machine used by the test (stellaris) has a variation of the cmsdk_apb_watchdog that locks INTEN when it is programmed to 1. The stellaris machine also does not reproduce the problem of the counter running out of cold reset due to the way the clocks are initialized. Signed-off-by: Roque Arcudia Hernandez Reviewed-by: Stephen Longfield --- tests/qtest/cmsdk-apb-watchdog-test.c | 214 ++++++++++++++++++++++++++ 1 file changed, 214 insertions(+) diff --git a/tests/qtest/cmsdk-apb-watchdog-test.c b/tests/qtest/cmsdk-apb-= watchdog-test.c index fe535a553c..3777b7bd59 100644 --- a/tests/qtest/cmsdk-apb-watchdog-test.c +++ b/tests/qtest/cmsdk-apb-watchdog-test.c @@ -68,6 +68,15 @@ static const CMSDKAPBWatchdogTestArgs machine_info[] =3D= { }, }; =20 +static void system_reset(QTestState *qtest) +{ + QDict *resp; + + resp =3D qtest_qmp(qtest, "{'execute': 'system_reset'}"); + g_assert(qdict_haskey(resp, "return")); + qobject_unref(resp); +} + static void test_watchdog(const void *ptr) { const CMSDKAPBWatchdogTestArgs *args =3D ptr; @@ -159,6 +168,199 @@ static void test_clock_change(const void *ptr) qtest_end(); } =20 +/* Tests the counter is not running after reset. */ +static void test_watchdog_reset(const void *ptr) +{ + const CMSDKAPBWatchdogTestArgs *args =3D ptr; + hwaddr wdog_base =3D args->wdog_base; + int64_t tick =3D args->tick; + g_autofree gchar *cmdline =3D g_strdup_printf("-machine %s", args->mac= hine); + qtest_start(cmdline); + g_assert_cmpuint(readl(wdog_base + WDOGRIS), =3D=3D, 0); + + g_assert_cmphex(readl(wdog_base + WDOGLOAD), =3D=3D, WDOGLOAD_DEFAULT); + g_assert_cmphex(readl(wdog_base + WDOGVALUE), =3D=3D, WDOGVALUE_DEFAUL= T); + + g_assert_cmphex(readl(wdog_base + WDOGCONTROL), =3D=3D, 0); + + /* + * The counter should not be running if WDOGCONTROL.INTEN has not been= set, + * as it is the case after a cold reset. + */ + clock_step(15 * tick + 1); + g_assert_cmphex(readl(wdog_base + WDOGLOAD), =3D=3D, WDOGLOAD_DEFAULT); + g_assert_cmphex(readl(wdog_base + WDOGVALUE), =3D=3D, WDOGVALUE_DEFAUL= T); + + /* Let the counter run before reset */ + writel(wdog_base + WDOGLOAD, 3000); + writel(wdog_base + WDOGCONTROL, 1); + + /* Verify it is running */ + clock_step(1000 * tick + 1); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 3000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 2000); + + system_reset(global_qtest); + + /* Check defaults after reset */ + g_assert_cmphex(readl(wdog_base + WDOGLOAD), =3D=3D, WDOGLOAD_DEFAULT); + g_assert_cmphex(readl(wdog_base + WDOGVALUE), =3D=3D, WDOGVALUE_DEFAUL= T); + + /* The counter should not be running after reset. */ + clock_step(1000 * tick + 1); + g_assert_cmphex(readl(wdog_base + WDOGLOAD), =3D=3D, WDOGLOAD_DEFAULT); + g_assert_cmphex(readl(wdog_base + WDOGVALUE), =3D=3D, WDOGVALUE_DEFAUL= T); + + qtest_end(); +} + +/* + * Tests inten works as the counter enable based on this description: + * + * Enable the interrupt event, WDOGINT. Set HIGH to enable the counter and= the + * interrupt, or LOW to disable the counter and interrupt. Reloads the cou= nter + * from the value in WDOGLOAD when the interrupt is enabled, after previou= sly + * being disabled. + */ +static void test_watchdog_inten(const void *ptr) +{ + const CMSDKAPBWatchdogTestArgs *args =3D ptr; + hwaddr wdog_base =3D args->wdog_base; + int64_t tick =3D args->tick; + g_autofree gchar *cmdline =3D g_strdup_printf("-machine %s", args->mac= hine); + qtest_start(cmdline); + g_assert_cmpuint(readl(wdog_base + WDOGRIS), =3D=3D, 0); + + g_assert_cmphex(readl(wdog_base + WDOGLOAD), =3D=3D, WDOGLOAD_DEFAULT); + g_assert_cmphex(readl(wdog_base + WDOGVALUE), =3D=3D, WDOGVALUE_DEFAUL= T); + + /* + * When WDOGLOAD is written to, the count is immediately restarted fro= m the + * new value. + * + * Note: the counter should not be running as long as WDOGCONTROL.INTE= N is + * not set + */ + writel(wdog_base + WDOGLOAD, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 4000); + clock_step(500 * tick + 1); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 4000); + + /* Set HIGH WDOGCONTROL.INTEN to enable the counter and the interrupt = */ + writel(wdog_base + WDOGCONTROL, 1); + clock_step(500 * tick + 1); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 3500); + + /* or LOW to disable the counter and interrupt. */ + writel(wdog_base + WDOGCONTROL, 0); + clock_step(100 * tick); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 3500); + + /* + * Reloads the counter from the value in WDOGLOAD when the interrupt is + * enabled, after previously being disabled. + */ + writel(wdog_base + WDOGCONTROL, 1); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 4000); + + /* Test counter is still on */ + clock_step(50 * tick + 1); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 3950); + + /* + * When WDOGLOAD is written to, the count is immediately restarted fro= m the + * new value. + * + * Note: the counter should be running since WDOGCONTROL.INTEN is set + */ + writel(wdog_base + WDOGLOAD, 5000); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 5000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 5000); + clock_step(4999 * tick + 1); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 5000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 1); + g_assert_cmpuint(readl(wdog_base + WDOGRIS), =3D=3D, 0); + + /* Finally disable and check the conditions don't change */ + writel(wdog_base + WDOGCONTROL, 0); + clock_step(10 * tick); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 5000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 1); + g_assert_cmpuint(readl(wdog_base + WDOGRIS), =3D=3D, 0); + + qtest_end(); +} + +/* + * Tests the following custom behavior: + * + * The Luminary version of this device ignores writes to this register aft= er the + * guest has enabled interrupts (so they can only be disabled again via re= set). + */ +static void test_watchdog_inten_luminary(const void *ptr) +{ + const CMSDKAPBWatchdogTestArgs *args =3D ptr; + hwaddr wdog_base =3D args->wdog_base; + int64_t tick =3D args->tick; + g_autofree gchar *cmdline =3D g_strdup_printf("-machine %s", args->mac= hine); + qtest_start(cmdline); + g_assert_cmpuint(readl(wdog_base + WDOGRIS), =3D=3D, 0); + + g_assert_cmphex(readl(wdog_base + WDOGLOAD), =3D=3D, WDOGLOAD_DEFAULT); + g_assert_cmphex(readl(wdog_base + WDOGVALUE), =3D=3D, WDOGVALUE_DEFAUL= T); + + /* + * When WDOGLOAD is written to, the count is immediately restarted fro= m the + * new value. + * + * Note: the counter should not be running as long as WDOGCONTROL.INTE= N is + * not set + */ + writel(wdog_base + WDOGLOAD, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 4000); + clock_step(500 * tick + 1); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 4000); + + /* Set HIGH WDOGCONTROL.INTEN to enable the counter and the interrupt = */ + writel(wdog_base + WDOGCONTROL, 1); + clock_step(500 * tick + 1); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 3500); + + /* + * The Luminary version of this device ignores writes to this register= after + * the guest has enabled interrupts + */ + writel(wdog_base + WDOGCONTROL, 0); + clock_step(100 * tick); + g_assert_cmpuint(readl(wdog_base + WDOGLOAD), =3D=3D, 4000); + g_assert_cmpuint(readl(wdog_base + WDOGVALUE), =3D=3D, 3400); + g_assert_cmphex(readl(wdog_base + WDOGCONTROL), =3D=3D, 0x1); + + /* They can only be disabled again via reset */ + system_reset(global_qtest); + + /* Check defaults after reset */ + g_assert_cmphex(readl(wdog_base + WDOGLOAD), =3D=3D, WDOGLOAD_DEFAULT); + g_assert_cmphex(readl(wdog_base + WDOGVALUE), =3D=3D, WDOGVALUE_DEFAUL= T); + g_assert_cmphex(readl(wdog_base + WDOGCONTROL), =3D=3D, 0); + + /* The counter should not be running after reset. */ + clock_step(1000 * tick + 1); + g_assert_cmphex(readl(wdog_base + WDOGLOAD), =3D=3D, WDOGLOAD_DEFAULT); + g_assert_cmphex(readl(wdog_base + WDOGVALUE), =3D=3D, WDOGVALUE_DEFAUL= T); + + qtest_end(); +} + int main(int argc, char **argv) { int r; @@ -172,10 +374,22 @@ int main(int argc, char **argv) qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_clock_change", &machine_info[MACHINE_LM3S811EVB], test_clock_change); + qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_reset", + &machine_info[MACHINE_LM3S811EVB], + test_watchdog_reset); + qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_inten_luminary", + &machine_info[MACHINE_LM3S811EVB], + test_watchdog_inten_luminary); } if (qtest_has_machine(machine_info[MACHINE_MPS2_AN385].machine)) { qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_mps2", &machine_info[MACHINE_MPS2_AN385], test_watchd= og); + qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_reset_mps2", + &machine_info[MACHINE_MPS2_AN385], + test_watchdog_reset); + qtest_add_data_func("/cmsdk-apb-watchdog/watchdog_inten", + &machine_info[MACHINE_MPS2_AN385], + test_watchdog_inten); } =20 r =3D g_test_run(); --=20 2.47.0.277.g8800431eea-goog