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Fri, 08 Nov 2024 09:38:45 -0800 (PST) X-Google-Smtp-Source: AGHT+IHRrXhlmPJ0n37QsRSInR5hhbtG4RSaFgNZqEa/TDwSmqv4aMq5b6+AU/3Qn/on13osz6JQaA== X-Received: by 2002:a05:600c:8715:b0:431:93d8:e1a1 with SMTP id 5b1f17b1804b1-432b751bcc2mr30817225e9.27.1731087525438; Fri, 08 Nov 2024 09:38:45 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Phil Dennis-Jordan , Roman Bolshakov Subject: [PULL 08/13] i386/hvf: Fix for UB in handling CPUID function 0xD Date: Fri, 8 Nov 2024 18:38:23 +0100 Message-ID: <20241108173828.111454-9-pbonzini@redhat.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241108173828.111454-1-pbonzini@redhat.com> References: <20241108173828.111454-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.34, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1731087623752116600 Content-Type: text/plain; charset="utf-8" From: Phil Dennis-Jordan The handling for CPUID function 0xD (supported XSAVE features) was improved in a recent patch. Unfortunately, this appears to have introduced undefined behaviour for cases where ecx > 30, as the result of (1 << idx) is undefined if idx > 30. Per Intel SDM section 13.2, the behaviour for ecx values up to and including 62 are specified. This change therefore specifically sets all registers returned by the CPUID instruction to 0 for 63 and higher. Furthermore, the bit shift uses uint64_t, where behaviour for the entire range of 2..62 is safe and correct. Signed-off-by: Phil Dennis-Jordan Link: https://lore.kernel.org/r/20241105155800.5461-3-phil@philjordan.eu Reviewed-by: Roman Bolshakov Signed-off-by: Paolo Bonzini --- target/i386/hvf/x86_cpuid.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/hvf/x86_cpuid.c b/target/i386/hvf/x86_cpuid.c index 3f16b0f363d..af9ee17a111 100644 --- a/target/i386/hvf/x86_cpuid.c +++ b/target/i386/hvf/x86_cpuid.c @@ -119,8 +119,8 @@ uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_= t idx, eax =3D 0; break; case 0xD: - if (!supported_xcr0 || - (idx > 1 && !(supported_xcr0 & (1 << idx)))) { + if (!supported_xcr0 || idx >=3D 63 || + (idx > 1 && !(supported_xcr0 & (UINT64_C(1) << idx)))) { eax =3D ebx =3D ecx =3D edx =3D 0; break; } --=20 2.47.0