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Fri, 08 Nov 2024 09:38:44 -0800 (PST) X-Google-Smtp-Source: AGHT+IFhGJcSaRqciiaNVKMg0EQCNyW/DKTtyrS2OAyPHgzj1mb0XaZIKay8rbT8rIU5KibEQwAjMA== X-Received: by 2002:a05:6000:1569:b0:37c:d2f0:7331 with SMTP id ffacd0b85a97d-381f1839aa8mr3196935f8f.0.1731087523745; Fri, 08 Nov 2024 09:38:43 -0800 (PST) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Phil Dennis-Jordan , Roman Bolshakov Subject: [PULL 07/13] i386/hvf: Integrates x2APIC support with hvf accel Date: Fri, 8 Nov 2024 18:38:22 +0100 Message-ID: <20241108173828.111454-8-pbonzini@redhat.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241108173828.111454-1-pbonzini@redhat.com> References: <20241108173828.111454-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.34, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1731087609897116600 From: Phil Dennis-Jordan Support for x2APIC mode was recently introduced in the software emulated APIC implementation for TCG. Enabling it when using macOS=E2=80=99s hvf accelerator is useful and significantly helps performance, as Qemu currently uses the emulated APIC when running on hvf as well. This change wires up the read & write operations for the MSR VM exits and allow-lists the CPUID flag in the x86 hvf runtime. Signed-off-by: Phil Dennis-Jordan Link: https://lore.kernel.org/r/20241105155800.5461-2-phil@philjordan.eu Reviewed-by: Roman Bolshakov Signed-off-by: Paolo Bonzini --- target/i386/hvf/x86_cpuid.c | 2 +- target/i386/hvf/x86_emu.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/target/i386/hvf/x86_cpuid.c b/target/i386/hvf/x86_cpuid.c index 492e8bfc809..3f16b0f363d 100644 --- a/target/i386/hvf/x86_cpuid.c +++ b/target/i386/hvf/x86_cpuid.c @@ -77,7 +77,7 @@ uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t = idx, ecx &=3D CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_MOVBE | - CPUID_EXT_POPCNT | CPUID_EXT_AES | + CPUID_EXT_POPCNT | CPUID_EXT_AES | CPUID_EXT_X2APIC | (supported_xcr0 ? CPUID_EXT_XSAVE : 0) | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND; ecx |=3D CPUID_EXT_HYPERVISOR; diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index 38c782b8e3b..be675bcfb71 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -663,6 +663,15 @@ static void exec_lods(CPUX86State *env, struct x86_dec= ode *decode) env->eip +=3D decode->len; } =20 +static void raise_exception(CPUX86State *env, int exception_index, + int error_code) +{ + env->exception_nr =3D exception_index; + env->error_code =3D error_code; + env->has_error_code =3D true; + env->exception_injected =3D 1; +} + void simulate_rdmsr(CPUX86State *env) { X86CPU *cpu =3D env_archcpu(env); @@ -677,6 +686,17 @@ void simulate_rdmsr(CPUX86State *env) case MSR_IA32_APICBASE: val =3D cpu_get_apic_base(cpu->apic_state); break; + case MSR_APIC_START ... MSR_APIC_END: { + int ret; + int index =3D (uint32_t)env->regs[R_ECX] - MSR_APIC_START; + + ret =3D apic_msr_read(index, &val); + if (ret < 0) { + raise_exception(env, EXCP0D_GPF, 0); + } + + break; + } case MSR_IA32_UCODE_REV: val =3D cpu->ucode_rev; break; @@ -777,6 +797,17 @@ void simulate_wrmsr(CPUX86State *env) case MSR_IA32_APICBASE: cpu_set_apic_base(cpu->apic_state, data); break; + case MSR_APIC_START ... MSR_APIC_END: { + int ret; + int index =3D (uint32_t)env->regs[R_ECX] - MSR_APIC_START; + + ret =3D apic_msr_write(index, data); + if (ret < 0) { + raise_exception(env, EXCP0D_GPF, 0); + } + + break; + } case MSR_FSBASE: wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data); break; --=20 2.47.0